2w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
1mo
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Verification Engineer Senior
Austin, Texas, United States
$191k-$269k/yr HybridFull Time
6+ YOEBachelor's in EE/CE/CS + 8+ yrs or Master's + 6+ yrs in ASIC/FPGA verification; SystemVerilog/UVM, OOP, coverage-driven verification, constrained-random testing, protocol experience (AXI, CHI, UART, SPI, I2C/I3C), strong debug skills.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium
1mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
3mo
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Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS with 10+ years in digital verification; SystemVerilog, UVM, Python/Perl; SOC/IP verification experience; strong communication.
SystemVerilog, UVM, Python, Perl, C/C++, Digital design, Scripting
1mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
2mo
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Staff Verification Engineer
Austin or Santa Clara
OnsiteFull Time
5+ YOE+5 years experience; BS/MS in CS/EE/CE; CPU verification; test plans and benches; IP verification; strong analytical skills.
SystemVerilog, C++, Python, Testbench
3mo
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Sr/Staff Design Verification Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's in EE/CE, 4+ years verification engineering experience (digital/analog/mixed-signal), 2+ years in custom or RTL verification flows, strong debug and communication skills, EM/SoC verification experience preferred.
Verilog, FastSpice, RTL2GDS, GenAI
1mo
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Senior Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBSEE+5yrs or MSEE+3yrs or PhD+1yr; expertise in Verilog/SystemVerilog, OVM/UVM, formal methods; knowledge of DDR, PCIe, AMBA; scripting in Python/Perl and UNIX/Linux; strong debugging and verification planning skills.
Verilog, SystemVerilog, VHDL, OVM/UVM, SystemVerilog assertions (SVA), DDR, PCIe, AMBA (CHI, ACE, AXI), AI/LLM, Python, Perl, UNIX/Linux
3w
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Director, Central AMS Verification
San Jose or Austin or Irvine
$170k-$340k/yr OnsiteFull Time
20+ YOE20+ years in mixed-signal SoC verification, Bachelor’s in CS/CE or related, expert in AMS verification methodologies (UVM, real-number modeling), Python automation, AI/ML for verification, and proven leadership building verification teams.
UVM, Python, Palladium, Veloce, Zebu
2mo
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Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
21h
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Silicon Design Verification Manager
Austin, Texas, United States
$192k-$278k/yr HybridFull Time
8+ YOE8+ years verification experience, degree in EE/CS/CE, expertise in advanced verification methodologies, processor architecture, System Verilog or C++, testbench design, and simulation-based verification.
System Verilog, C++
5d
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Verification Representative (Remote) - NC
Charlotte or Texas or Tennessee or North Carolina or Utah or Florida
$16/hr RemotePart Time
Conduct high-volume inbound/outbound verification calls, maintain attention to detail, pass background check, and be authorized to work in the U.S.; secure hardwired high-speed internet required.
Dugout
3mo
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Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
0+ YOEBachelor/Master/PhD in Electrical/Computer Engineering or related field; 2+ years with Bachelors; strong HDL/SystemVerilog/UVM; ASIC/silicon verification experience.
Verilog, VHDL, SystemVerilog, UVM
1d
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Insurance Verification Specialist
San Antonio, Texas, United States
HybridFull Time
2+ YOEVerify patient insurance and benefits, update registration, obtain referrals/authorizations, navigate verification tools, EPIC and Microsoft Office proficiency, HS diploma required.
Microsoft Office, EPIC
1mo
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Insurance Verification Specialist
Granbury, Texas, United States
OnsiteFull Time
1+ YOE1 year medical insurance verification experience required; high school diploma; update patient demographics, verify benefits and authorizations, determine patient financial responsibility.
6d
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Design Verification Engineer | Sensing
Dallas, Texas, United States
OnsiteFull Time
5+ YOEMasters in EE,5+ years experience in digital/AMS verification for mixed-signal chips, strong SystemVerilog skills, robust DV flow knowledge, experience with verification closure and debugging.
SystemVerilog, Cadence, ATPG, BIST, VBOX, IDDQ
1mo
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Insurance Verification Specialist
Midland, Texas, United States
OnsiteFull Time
1+ YOE1–2 years experience in healthcare insurance billing/verification/collections/authorizations; knowledge of medical terminology, computer systems and spreadsheets; strong communication and problem-solving skills.
3w
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
1mo
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Senior Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
4+ YOEExpert SystemVerilog and UVM skills, testbench development, verification planning, scripting (Python, Perl, TCL), mixed-signal verification, debugging, and technical leadership; Bachelor’s required, 4+ years relevant experience.
SystemVerilog, UVM, Python, Perl, TCL
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