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569 asic engineer jobs at 91 companies in Burbank, CA

3d
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
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3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
3+ YOEDesign engineer with strong Verilog/SystemVerilog, ASIC design, RTL timing and verification experience.
Verilog, SystemVerilog, RTL, EDA tools, Python, Perl
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1mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
Butterfly Network
Butterfly NetworkNYSE: BFLY: Handheld whole-body ultrasound scanners powered by semiconductor technology.
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
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2mo
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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
Ayar Labs
Ayar Labs: Develops optical interconnect technology for high-speed data movement.
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
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Senior ASIC Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
2+ YOE2+ years ASIC verification experience, UVM experience, ability to build UVM testbenches, knowledge of digital logic, SoC architecture, AMBA protocols, scripting, and verification strategy.
UVM, ARM, AMBA, AHB, AXI
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ASIC Design Engineer
Santa Clara or United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
3+ YOEBachelor's degree with 3+ years of ASIC design experience; memory subsystem and RTL knowledge beneficial.
RTL, HDL, DFI, DRAM, Memory subsystem, Performance simulators
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
3+ YOEDesign ASICs using Verilog/SystemVerilog; strong digital design, timing, RTL, verification, and collaboration with cross-functional teams.
Verilog, SystemVerilog, EDA tools, Synthesis, Lint, Perl, Python
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1w
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ASIC Implementation Engineer STA
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
12+ YOEBachelor's in EE or Computer Engineering, 12+ years ASIC STA experience, proficiency with Cadence or Synopsys sign-off flows, SDC/constraint development, and scripting in Tcl, Python, or Perl.
Tcl, Python, Perl, Shell, Cadence, Synopsys
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2mo
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ASIC Design Engineer lll
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
4+ YOEBachelor's in electrical engineering; 4+ years in ASIC/SoC design; strong Verilog/SystemVerilog; experience with EDA tools; good communication; Perl/Python a plus; AI tool experience a plus.
Verilog, SystemVerilog, EDA tools, Perl, Python
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Senior ASIC Design Engineer
Santa Clara or United States
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOE5+ years ASIC or SoC design experience; BS/MS in relevant engineering or equivalent; RTL design, logic synthesis, timing analysis, SOC integration experience; strong scripting/programming (Perl, Python, C++).
Perl, Python, C++
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
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1mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
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3mo
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Sr. Staff ASIC Verification Engineer
Palo Alto, California, United States
$237k-$296k/yr OnsiteFull Time
Rivian
RivianNASDAQ: RIVN: Designs and manufactures electric vehicles and charging networks.
10+ YOETypically 10+ years in ASIC design verification; BS/MS or PhD in Electrical or Computer Engineering; deep computer architecture; NoC; UPF/CPF; Systolic Arrays/NPUs; CNN/Transformer mapping; compilers/toolchains.
SystemVerilog, UVM, SVA, ISO 26262, FIA, Emulation, FPGA
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SR ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
1+ YOEDegree in electrical/computer engineering or related plus multi-year ASIC verification experience; proficiency in System Verilog and UVM; ASIC verification, simulation, emulation, post-silicon debug experience; Linux and programming (C/C++, Python/Perl).
System Verilog, UVM, Veloce, Palladium, Zebu, HAPS, Linux, C/C++, Python/Perl
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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
Nokia
NokiaNYSE: NOK: Sells telecommunications infrastructure and software for global network operators.
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
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1mo
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Sr. ASIC Verification Engineer
Sunnyvale or Munich
OnsiteFull Time
Tensordyne
Tensordyne: Designs AI chips and systems for efficient model inference.
4+ YOE4+ years ASIC verification experience; expert in SystemVerilog/UVM, constraint-random and coverage-driven verification; experience with C/C++/SystemC, high-speed interfaces, scripting (Python/Perl/TCL/Shell), and post-silicon validation; BS required, MS preferred.
SystemVerilog, UVM, C, C++, SystemC, Python, Perl, TCL, Shell, ARM, RISC-V, PCIe, Ethernet, DDR, HBM, SerDes
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3mo
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ASIC/SoC Design Engineer
San Jose or United States
$146k-$250k/yr OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in ASIC/SoC design, RTL/verification, Verilog/SystemVerilog, timing constraints, PD integration, DFT, and cross-domain collaboration.
Verilog, SystemVerilog, SystemVerilog Assertions, SDC timing constraints, ASIC CAD tools, AMBA AXI/AXI-S/APB, UPF, Perl, Python, Makefile
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3mo
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ASIC Validation Engineer
Bay Area, California, United States
$168k-$297k/yr RemoteFull Time
Block
BlockNYSE: XYZ: Creates financial tools for businesses and individuals.
4+ YOEBachelor's in Electrical Engineering; 4+ years in silicon/hardware validation; lab experience; scripting (Python); cross-functional collaboration.
Python, lab equipment, oscilloscopes, logic analyzers, power supplies, SPI, I2C, JTAG, UART
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3mo
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ASIC Design Verification Engineer
Santa Clara, California, United States
$106k-$172k/yr OnsiteFull Time
Palo Alto Networks
Palo Alto NetworksNASDAQ: PANW: Provides enterprise-grade network, cloud, and endpoint security software.
3+ YOEBS in EE, CE, or CS; minimum 3 years ASIC verification; SystemVerilog/UVM; test plans, coverage, and debug; Python automation; strong collaboration.
SystemVerilog, UVM, Python, C++, Perl, UNIX Shell
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1mo
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ASIC/FPGA Design Engineer III
Denver or Highlands Ranch or Sunnyvale or Cambridge
$101k-$201k/yr OnsiteFull Time
Lockheed Martin
Lockheed MartinNYSE: LMT: Designs and manufactures global security and aerospace systems.
3+ YOEUS citizen able to obtain DoD Secret clearance, BS in Electrical Engineering (or equivalent), 3+ years professional FPGA development, HDL experience (VHDL/Verilog/SystemVerilog), and experience across ASIC/FPGA lifecycle.
VHDL, Verilog, SystemVerilog, Linux, AMD/Xilinx Vivado, Microchip Libero, Microsoft Project, JIRA, Earned Value Management System (EVMS)
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