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Sr. ASIC Design Engineer (Starshield)
Hawthorne, California, United States
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical or computer engineering or computer science; 5+ years RTL/FPGA/ASIC experience.
Verilog, SystemVerilog, RTL, FPGA, ASIC, Python, TCL, EDA tools (HDL simulators: VCS, Questa, IES), Spyglass, Xilinx Vivado, Quartus II, AXI, AHB
3mo
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Principal ASIC Design Engineer (Starshield)
Hawthorne, California, United States
$200k-$285k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE/CS; 8+ years RTL/FPGA/ASIC; Verilog/SystemVerilog; experience with ASICs/FPGA; scripting (Python, TCL).
Verilog, SystemVerilog, VCS, Questa, IES, Spyglass, Xilinx Vivado, Altera Quartus II, Python, TCL
2w
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Senior ASIC Package Design Engineer
Los Angeles or United States
$180k-$260k/yr RemoteFull Time
5+ YOEBachelor's in engineering, 5+ years ASIC package design experience (FC-BGA), expertise in substrate technologies, SI/PI and thermal management, experience with OSATs and package qualification.
SIWave, HFSS, ADS
3w
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ASIC Design Verification Engineer
Los Angeles or United States
$130k-$200k/yr OnsiteFull Time
3+ YOEB.S./M.S. in EE/CE or related, 3+ years ASIC/SoC verification experience, SystemVerilog/UVM/SVA, simulation and waveform tools (VCS, Xcelium, Questa, Verdi, SimVision), scripting (Python/Perl/TCL), and Git.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, APB, AHB, AXI
3w
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Principal ASIC Design Verification Engineer
United States or Los Angeles
$190k-$285k/yr OnsiteFull Time
10+ YOEB.S. or M.S. in EE/CE or related, 10+ years ASIC/SoC verification, strong SystemVerilog/UVM and SVA skills, experience with VCS/Xcelium/Questa and Verdi/SimVision, scripting (Python/Perl/TCL), Git, CI/CD, C/C++, and ITAR U.S. person eligibility.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, C, C++, CI/CD
3mo
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Principal ASIC Package Design Engineer
Los Angeles or United States
$200k-$280k/yr RemoteFull Time
10+ YOELead ASIC package design for FC-BGA and MCM; 10+ years; OSATs experience; SI/PI; thermal management; collaborate with silicon, RF, and systems teams.
SIWave, HFSS, ADS
3w
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Senior ASIC Design Verification Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOEB.S. or M.S. in EE/CE or related field; 5+ years ASIC/SoC verification; strong SystemVerilog, UVM, SVA, simulation and waveform-debug skills; scripting (Python/Perl/TCL), Git, CI/CD, and familiarity with APB/AHB/AXI and C/C++; must be a U.S. person or eligible for export license.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, CI/CD, C, C++, APB, AHB, AXI
1mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
1mo
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Principal ASIC Design Verification Engineer - Terawave
Texas or Seattle or Los Angeles or California or United States
$269k-$377k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
12+ YOE12+ years ASIC/SoC verification experience, BS/MS/PhD in EE/CE or related, expert in System Verilog and UVM, strong technical leadership, experience with complex communication signal-processing hardware.
System Verilog, UVM
1mo
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Senior ASIC Design Verification Engineer - Terawave
Texas or Seattle or Los Angeles or California
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, assertions, coverage closure, RTL/testbench debugging, cross-functional collaboration; must meet U.S. employment eligibility.
System Verilog, UVM
3w
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Sr. ASIC Design Verification Engineer, Amazon Leo
Sunnyvale or San Diego or Los Angeles County
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/CE/EE, 7+ years verification experience (communications preferred), 5+ years with UVM and C/C++ and scripting, familiarity with Matlab and formal verification preferred; must meet U.S. export-control eligibility.
UVM, SystemC, DPI-C, Matlab, C/C++, FPGA
6d
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Principal Digital Engineer
Woodland Hills, California, United States
$125k-$188k/yr OnsiteFull Time
5+ YOEU.S. citizen with active Secret clearance; extensive experience in high-speed digital design and verification, FPGA/SoC/ASIC implementation (VHDL/Verilog), hardware requirements and verification processes.
VHDL, Verilog, System Verilog, UVM, MATLAB, Simulink, Hardware-In-Loop, FPGA, SoC, ASIC, DO-254
1w
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Senior Principal Digital Engineer
Los Angeles, California, United States
$156k-$235k/yr OnsiteFull Time
8+ YOEU.S. citizen with active Secret clearance. Requires extensive high-speed digital design and verification experience, FPGA/SoC/ASIC implementation skills (VHDL/Verilog), and STEM degree with significant experience.
VHDL, Verilog, System Verilog, UVM, MATLAB, Simulink, FPGA, SoC, ASIC, Electronic Hardware-In-Loop
1w
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Senior Principal Digital Engineer
Woodland Hills, California, United States
$156k-$235k/yr OnsiteFull Time
4+ YOEU.S. citizen with active Secret clearance; STEM degree (BS/MS/PhD) with relevant experience (min 4+ yrs depending on degree); experience in high-speed digital design, FPGA/SoC/ASIC (VHDL/Verilog), design verification, and hardware implementation.
VHDL, Verilog, System Verilog, UVM, FPGA, SOC, ASIC, MATLAB, Simulink, Hardware-In-Loop, DO-254
1mo
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Electrical Engineer III/IV
Burbank, California, United States
$125k-$177k/yr OnsiteFull Time
8+ YOEBA/BS in engineering, 8+ years relevant experience, US Person required for ITAR work, expertise in analog/digital/micro-electronics, VHDL, ASIC, DO-254/DO-160, magnetics, switching power supplies, hardware/software integration, and strong communication skills.
VHDL, DO-254, DO-160, Kaizen, 5S, Lean
6d
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Principal Digital Engineer
Los Angeles, California, United States
$125k-$188k/yr OnsiteFull Time
5+ YOEU.S. citizen with active Secret clearance, STEM degree plus relevant experience (Bachelor+5yrs/Master+3yrs/PhD+1yr), experience in high-speed digital design, FPGA/SoC/ASIC and verification, EMV/V&V tools, strong communication.
VHDL, Verilog, System Verilog, System Verilog (UVM), UVM, MATLAB, Simulink
1w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
1w
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Manager Digital Engineering 2
Woodland Hills, California, United States
$161k-$242k/yr OnsiteFull Time
6+ YOESTEM degree with 6–8+ years relevant experience, experience leading technical teams, digital design/verification knowledge (FPGA/SoC/ASIC), PLM experience, ability to obtain/maintain U.S. security clearance, U.S. citizenship required.
FPGA, SoC, ASIC, Product Lifecycle Management (PLM), Siemens Teamcenter Enterprise, Teamcenter Unified Architecture (UA), Tc AW \u00096 Active Workspace, System Verilog, UVM, Hardware-In-Loop, MATLAB, Simulink, DO-254, RCCAs, BOE, EMV S
1w
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Manager Digital Engineering 2
Los Angeles, California, United States
$161k-$242k/yr OnsiteFull Time
6+ YOEU.S. citizen able to obtain security clearance; STEM bachelor's + 8 years or master's + 6 years; experience leading technical teams in digital design (FPGA/SoC/ASIC); PLM and cost estimating experience; strong communication skills.
PLM, Siemens Teamcenter Enterprise, Teamcenter Unified Architecture (UA), Tc AW – Active Workspace, MATLAB, Simulink, System Verilog, UVM, Hardware-In-Loop
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