19 asic engineer jobs at 9 companies in Stockton, CA
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
1w
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AI/ML ASIC Architect
Milpitas, California, United States
$137k-$226k/yr HybridFull Time
3+ YOEBS+7/MS+5/PhD+3 experience in CE/EE with ASIC/SoC architecture experience; authoring architecture specs; PCIe/UCIe/CXL and DMA subsystems; ML/LLM and accelerator knowledge required.
UCIe, PCIe, CXL, DMA, HBM, NoC, FPGA, MX format, CUDA, NVLink, InfiniBand, RDMA, NVMe, NAND, AXI
1w
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AI/ML ASIC Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
15+ YOEBachelors (or Masters/PhD) in Computer/Electrical Engineering with 15+ years architecture experience; deep expertise in PCIe/UCIe/CXL, DMA, SoC, HBM, ML/AI accelerator architecture; strong microarchitecture and system-level design skills.
UCIe, PCIe, CXL, DMA, NoC, FPGA, RTL, DV, Simulation, Emulation, Firmware, HBM, CUDA, NVLink, InfiniBand, RDMA, NVMe, NAND, AXI, MX format
1w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
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Digital Verification Engineer - Weapon Subsystems 2
Livermore or California or New Mexico or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's degree or equivalent, ability to obtain DOE Q-level (Top Secret) clearance, several years applying formal verification to FPGA/ASIC, proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA), strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
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Software Engineering Technical Leader
Milpitas, California, United States
$211k-$305k/yr HybridFull Time
5+ YOEDegree in CS/EE/Electronics (or related) with considerable experience (varies by degree), strong expertise in C/C++ and Linux, experience with coherent optics, PHY/SerDes, ASIC/NPU, DSP, CMIS/SFF familiarity, proven architecture and cross-functional leadership.
C, C++, Linux, CMIS, SFF, Cisco Silicon One, IOS-XR, SONiC, FBOSS, DSP, ASIC, NPU, PHY, SerDes, FEC, ZR, OpenZR+, DWDM
22h
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Associate Engineer - Firmware
Pleasanton, California, United States
$107k-$141k/yr OnsiteFull Time
Bachelor's or master's degree in electrical engineering, computer engineering, or computer science; C/C++ embedded firmware, RTOS or bare-metal, Python or Perl, lab equipment, debugging, and U.S. work authorization required.
C, C++, Python, Perl, RTOS, GitHub, ST microcontrollers, ASIC, oscilloscopes, function generators, voltmeters, debuggers, simulation tools, PID, TCP, UDP, UART, SPI, I2C, Assembly, lwIP, SoC, FPGA
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Senior Software Engineer - VSD - Freemont CA Hybrid
Fremont, California, United States
$130k-$233k/yr HybridFull Time
10+ YOEMS in EE/CE/CS,10+ years designing and deploying optimization algorithms for EDA, ASIC/FPGA expertise, proficiency in C/C++ and Python, strong software engineering and communication skills.
C, C++, Python
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SSD Architect
San Jose or Rancho Cordova or Longmont or Vancouver
$196k-$314k/yr HybridFull Time
5+ YOEBachelor's in computer engineering or computer science, 5+ years in embedded systems architecture with ASIC and/or firmware experience; SSD domain expertise, system-level architecture, and cross-functional leadership.
PCIe, NVMe, ASIC
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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SSD Architect
Longmont or Rancho Cordova or San Jose or Vancouver
$196k-$314k/yr HybridFull Time
5+ YOEBachelor's in Computer Engineering/Computer Science, 5+ years in embedded systems/ASIC or firmware architecture, SSD domain expertise (PCIe/NVMe, memory controller), strong cross-functional leadership and system-level design experience.
PCIe/NVMe, ASIC, firmware
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SSD Architect
Vancouver or San Jose or Longmont or Rancho Cordova
$185k-$289k/yr HybridFull Time
5+ YOEBachelor's in Computer Engineering/CS, 5+ years in embedded systems architecture with ASIC and/or firmware experience; deep SSD domain knowledge (PCIe/NVMe, memory controller), system-level trade-offs, and cross-functional leadership.
PCIe, NVMe, ASIC, firmware
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Software Engineering Technical Leader
Milpitas, California, United States
$184k-$264k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CS (10+ yrs) or Master's (8+ yrs); experience with C, C++, Python, Linux, device drivers, embedded systems, and ASIC/FPGA bring-up; experience with Sonic/ONIE/BMC/IPMI/Redfish; strong debugging and communication skills.
C, C++, Python, Linux, Sonic, ONIE, BMC, IPMI, Redfish, GDB, KGDB, CMIS, SFF, SFP, QSFP, I2C, SPI, UART, PCIe, GPIO
1mo
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Hardware Systems Engineering Technical Leader
Milpitas, California, United States
$169k-$241k/yr OnsiteFull Time
3+ YOEBachelor/Master/PhD in EE or CE with 3–8+ years experience; expertise in high-speed Ethernet/PCIe, board design and bring-up, Cadence/Allegro, lab validation, and cross-functional collaboration.
Cadence, Allegro, Concept, Serdes, PCIe, Ethernet, ASIC, FPGA, CPLD, DDR4, DDR5, MDIO, SPI, I2C
2mo
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SSD Architect
Rancho Cordova or San Jose or Longmont or Vancouver
$196k-$314k/yr HybridFull Time
5+ YOEBachelor's in a technical discipline, 5+ years in embedded systems architecture with ASIC and/or firmware experience, deep SSD-domain expertise, strong cross-functional leadership, and system-level design skills.
3mo
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Software Engineering Technical Leader, Ethernet Switching
Milpitas, California, United States
$184k-$264k/yr HybridFull Time
10+ YOEBS+10 years or MS+8 years or PhD+6 years in C/C++ and Python; embedded/router/switch software; debugging with GDB; SDLC and L2/L3/ACL/QOS; SDK development on networking ASICs; traffic generators (IXIA/Spirent).
C, C++, Python, GDB, SDK, IXIA, Spirent, Networking ASICs, NPU, DPU
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE,12+ years ARM CPU SoC/ASIC architecture experience, Ethernet/PCIe and memory subsystem expertise, EM/thermal tradeoff and IP selection experience, scripting in Tcl/Perl/Python preferred.
Tcl, Perl, Python
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