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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
3d
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Project Lead ASIC Engineer
Cambridge, Massachusetts, United States
$95k-$245k/yr HybridFull Time
5+ YOEBachelor's in engineering required (masters preferred); 5+ years ASIC hardware engineering experience with bachelor's (less with advanced degrees); ability to design/simulate transistor-level circuits, lead small teams, and work with fabrication/test sites.
3mo
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ASIC Design Engineer
Irvine or Andover
$108k-$173k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical Engineering with 8+ years of related experience or Master's in Electrical Engineering with 6+ years of related experience; ASIC implementation, synthesis, DFT, floorplanning, place & route, clocking, power planning and analysis, timing closure, signal integrity, physical design checks.
EDA tools, Synthesis tools, Place and Route (P&R) tools, Floorplanning tools, Clocking/Timing analysis tools, Power analysis tools
1mo
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ASIC/FPGA Design Engineer III
Denver or Highlands Ranch or Sunnyvale or Cambridge
$101k-$201k/yr OnsiteFull Time
3+ YOEUS citizen able to obtain DoD Secret clearance, BS in Electrical Engineering (or equivalent), 3+ years professional FPGA development, HDL experience (VHDL/Verilog/SystemVerilog), and experience across ASIC/FPGA lifecycle.
VHDL, Verilog, SystemVerilog, Linux, AMD/Xilinx Vivado, Microchip Libero, Microsoft Project, JIRA, Earned Value Management System (EVMS)
2mo
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ASIC Digital Design Engineer-17369
Boxborough or Markham or Mississauga or Ottawa
$138k-$208k/yr OnsiteFull Time
Experienced ASIC digital designer/verifier with Verilog, Perl, Tcl, and Python skills; knowledge of RTL design/verification, static timing analysis, synthesis, simulation, and debugging; HBM/DDR protocol experience preferred.
Verilog, Perl, Tcl, Python
1mo
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Senior ASIC Front End Infrastructure Engineer
Santa Clara or Westford or Austin or Durham
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years experience; Masters in Electrical Engineering, Computer Engineering, Computer Science or related; Python/Perl; AI tooling; Make; CI (Jenkins); strong problem solving; ASIC/CPU verification knowledge.
Python, Perl, Make, Jenkins
1mo
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Senior ASIC Timing Engineer
Westford or Durham
$168k-$311k/yr OnsiteFull Time
4+ YOEBS in ECE (8+ yrs) or MS (4+ yrs) in synthesis and timing; hands-on STA, timing constraints, ECOs, physical design and synthesis/LEC; experience with Synopsys PrimeTime or Cadence Tempus; Python, Tcl, Make scripting.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Make
2mo
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Mixed Signal ASIC Engineer
Boston, Massachusetts, United States
OnsiteFull Time
5+ YOEPhD in electrical engineering or equivalent industry experience; 5+ years designing analog/mixed-signal ICs; strong ADC/DAC, amplifiers; tape-out experience; Cadence or Synopsys tools; end-to-end IC development.
Cadence, Synopsys
3w
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Principal Digital Design Engineer (ASIC)
Somerset or Wilmington
$160k-$239k/yr OnsiteFull Time
10+ YOE10+ years ASIC/SoC digital design experience, Bachelor’s degree in EE/CE, expertise in SystemVerilog/Verilog, RTL design, synthesis, timing closure, MATLAB/TCL/Python modeling, Cadence tools, and tapeout experience.
SystemVerilog, MATLAB, Verilog, Python, TCL, Cadence, UVM
1mo
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
3mo
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ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA) (North Reading, MA, US)
North Reading, Massachusetts, United States
$99k-$158k/yr OnsiteFull Time
3+ YOE3+ years in digital logic verification; Cadence Xcelium; SystemVerilog and UVM; IP protocols (SPI/AXI/DDR); RTL Verilog; CI/CD workflows.
Cadence Xcelium, SystemVerilog, UVM, Verilog HDL, CI/CD
1mo
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Member of Technical Staff, ASIC Architecture
Santa Clara or Boston
OnsiteFull Time
5+ YOEBS/MS/PhD in Electrical Engineering or Computer Science with 5+ years of relevant experience; strong memory systems and architecture background.
Performance modeling tools, Circuit design tools, GPU memory modeling
3w
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
2mo
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Timing Design Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years ASIC timing constraints, STA flow, scripting (Tcl/Perl); experience with synthesis, DFT, backend; strong communication.
Primetime, Tcl, Perl, Synthesis tools
2w
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Senior Electrical Engineer
Wilmington, Massachusetts, United States
$115k-$173k/yr OnsiteFull Time
5+ YOEBS/MS in Electrical Engineering, 5+ years product development experience, motion control required, embedded microprocessors, PCB layout (Altium) experience, firmware/FPGA/Verilog knowledge, ability to support system-level design and testing.
PCB Layout Tools, Altium, PLD, FPGA, ASIC, Verilog
2w
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Electrical Engineer - Hardware & Embedded Systems
Waltham, Massachusetts, United States
$100k-$116k/yr OnsiteFull Time
4+ YOEBachelor's in electrical/computer engineering, 4+ years relevant experience, 3+ years embedded systems, proficiency in Embedded C/C++, RTOS, hardware-software integration, control systems, and communication protocols (I2C, SPI, UART, CAN).
Embedded C/C++, RTOS, I2C, SPI, UART, CAN, MATLAB/Simulink, LabVIEW, PLCs, FPGA, ASIC, Git, IDEs, debuggers
1mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOEBS/ MS in Electrical/Computer Engineering; 7+ years ASIC/SoC verification; strong CXL/CHI/AXI; SystemVerilog/UVM; cache-coherent systems; test plans, coverage; Python scripting.
SystemVerilog, UVM, Python
1w
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Principal FPGA Digital Design Engineer - Sign-on Bonus
Nashua, New Hampshire, United States
OnsiteFull Time
6+ YOESecret-clearable engineer with 6+ years FPGA/ASIC experience, VHDL/Verilog RTL coding, timing closure, lab debug, familiarity with high-speed interfaces and revision control.
VHDL, Verilog, Xilinx Vivado, Intel/Altera Quartus, ChipScope, SignalTap, ILA, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, Matlab, Simulink, UVM, SystemVerilog, C, C++
2mo
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FPGA Design Engineer
Nashua or Manchester or New Hampshire or United States
$97k-$165k/yr OnsiteFull Time
4+ YOEEligible for Secret clearance; typically a Bachelor's + 4+ years (or equivalent). FPGA/ASIC design experience with VHDL/Verilog, testbench development, timing closure, revision control, lab testing, and strong communication/problem-solving skills.
VHDL, Verilog HDL, SystemVerilog, UVM, GIT, CVS, Clearcase, Subversion, Xilinx Vivado, Intel/Altera Quartus, ModelSim, QuestaSim, MATLAB/Simulink, Perl, Tcl, Python, shell, C/C++, ILA, ChipScope, SignalTap
3w
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Engineer: Sr. Electrical Design Engineer
Cambridge, Massachusetts, United States
$80k-$110k/yr OnsiteFull Time
5+ YOEMaster's in EE, 5+ years product development experience, PCB and embedded hardware design, Altium/Eagle, C/Assembly, verification/validation, FDA/ISO 13485 experience, LabVIEW/MATLAB/Simulink familiarity.
Altium, Autodesk Eagle, C, Assembly, Verilog, VHDL, FPGA, ASIC, LabVIEW, MATLAB, Simulink, Java, Android, oscilloscopes, logic analyzers
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