3mo
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RTL Design Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design experience; Verilog/SystemVerilog; front-end tools; mixed-signal and analog concepts; scripting (Perl, JSON, Python); GenAI tooling for RTL design.
Verilog, SystemVerilog, Verilog simulators, UPF, Python, Perl, JSON
3w
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Interconnect Micro-architect/RTL Design Engineer
Austin or Boxborough
$156k-$268k/yr HybridFull Time
Experienced RTL design engineer with strong Verilog/System Verilog skills, knowledge of C/C++ and scripting (Perl or Python), digital/high-speed design understanding, and experience with multi-processor coherency, DFT-friendly RTL and post-silicon debug.
Verilog, System Verilog, C, C++, Perl, Python, x86, ARM
3mo
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Senior Staff RTL Design Engineer- 16908
Boxborough, Massachusetts, United States
$138k-$208k/yr OnsiteFull Time
10+ YOE10+ years ASIC digital design experience with production RTL ownership, Verilog and Perl proficiency, knowledge of synthesis, timing analysis, and power optimization; Bachelor's degree in EE/CE or related field required.
Verilog, Perl
2mo
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RTL Design Engineer (North Reading, MA, US)
North Reading, Massachusetts, United States
$123k-$197k/yr OnsiteFull Time
5+ YOEBSEE or MSEE with 5+ years; extensive RTL Verilog; CDC/STA; memory/serial interfaces; scripting (Python, Tcl, Make).
Verilog, Python, Tcl, Make
2mo
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Senior Engineer, Digital Design Engineering
Wilmington, Massachusetts, United States
$124k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital/mixed-signal design and verification; proficiency with RTL, Verilog/SystemVerilog; experience with Cadence or Synopsys tools.
Verilog, SystemVerilog, RTL, Cadence, Synopsys
6d
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$206k-$251k/yr OnsiteFull Time
Expertise in interconnect, cache/coherency and RTL generator design; strong software engineering and hardware RTL skills; BS/MS in EE/CE/CS or equivalent experience.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Bluespec, Git, Github, Jira, Confluence, TileLink, RISC-V, AXI, AHB, APB, CHI
1mo
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FPGA Engineer
Boston, Massachusetts, United States
OnsiteFull Time
RTL proficiency (Verilog or VHDL), real industry FPGA deployment experience, familiarity with major FPGA platforms (Xilinx/AMD, Lattice, Intel/Altera), embedded C/C++ experience, and experience with prototype bring-up and ASIC verification workflows.
Verilog, VHDL, C, C++, RTL, FPGA, Xilinx, AMD, Lattice, Intel/Altera, ASIC, ADC, DAC
1mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
1w
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General Support Engineer – Aerospace, Defense & Government (ADG)
Portsmouth, New Hampshire, United States
$96k-$139k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CE,3+ years hardware support or board-level engineering,FPGA and RTL (Verilog/SystemVerilog) experience,lab debug with oscilloscopes/logic/protocol analyzers,Tcl/Python/Java scripting,eligible for U.S. security clearance.
Verilog, SystemVerilog, RTL, DDR, PCIe, Ethernet, Oscilloscope, Logic Analyzer, Protocol Analyzer, Tcl, Python, Java, FPGA
2mo
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FPGA Engineer (MA, Boston)
Boston, Massachusetts, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, HDL, C/C++, Python; VHDL/Verilog; hardware security; IP core development; FPGA toolchains; Xilinx/Intel devices; simulation and verification; system integration; embedded software testing; cryptography; cocotb/pyuvm.
RTL, VHDL, Verilog, Python, C, C++, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, Xilinx, FPGA verification tools, cocotb, pyuvm
1mo
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Staff Engineer, Design Verification
Westborough, Massachusetts, United States
$128k-$189k/yr OnsiteFull Time
2+ YOEBachelor's/Master's/PhD in CS/EE or related; 2–5 years verification experience; strong UVM, constrained-random, coverage, SVA, RTL simulation, C/C++, Python/Perl, and Linux skills.
UVM, SVA, RTL, C/C++, Python, Perl, Linux, AMBA, PCIe, Ethernet
2mo
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Principal Firmware/FPGA Engineer (Onsite)
Cambridge, Massachusetts, United States
$108k-$205k/yr OnsiteFull Time
8+ YOE8+ years in STEM or an advanced degree with 5+ years; FPGA RTL/Verilog/VHDL; DSP fundamentals; high-speed interfaces; scripting; ability to obtain security clearance
Verilog, VHDL, RTL, FPGA, C++, Python, bash, Tcl, Ethernet, sFPDP, HBM2, DDR, Linux, Petalinux
1mo
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
1mo
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Modem HW Design Verification Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$128k-$192k/yr OnsiteFull Time
1+ YOEDegree in computer/electrical engineering or related field (BS/MS/PhD) with 1+ years (MS) or 2+ years (BS) engineering experience. Experience in verification planning, SystemVerilog/UVM, RTL languages, C/C++, Python/Perl, Unix/Linux scripting, and GenAI/ML-assisted verification preferred.
SystemVerilog, UVM, OVM, Verilog, VHDL, C, C++, SystemC, Python, Perl, Unix/Linux shell scripting, Makefiles, XML, RTL
1mo
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Sr. FPGA Engineer
Marlborough, Massachusetts, United States
OnsiteFull Time
5+ YOEBachelor's in Engineering required (Master's preferred), 5+ years FPGA RTL experience with Verilog/SystemVerilog, 3+ years software development (C/C++/C#/Python), experience with QuestaSim, Vivado, Quartus, Git/CI-CD, ARM/Linux integration; MATLAB/DSP desirable.
Verilog, SystemVerilog, C, C++, C#, Python, QuestaSim, Vivado, Quartus, MATLAB, ARM, Linux, Git, CI/CD
1mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
2w
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Senior Engineer (Andover, MA)
Andover, Massachusetts, United States
$101k-$111k/yr HybridFull Time
Bachelor's in CS/CE or related; experience/coursework in digital/electronics design and verification, MATLAB/Python, SPICE/Simetrix/SIMPLIS/NL5, Verilog/SystemVerilog, UVM, RTL simulators, FPGA emulation, ARM/C, scripting (Perl/Tcl/Python), STA and UPF constraints.
Matlab, Python, Spice, Simetrix, SIMPLIS, NL5, Verilog, SystemVerilog, Xcelium, ModelSim, NCsim, UVM, FPGA emulators, ARM, C, Perl, Tcl, Unix, Linux, STA, UPF
1w
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Principal FPGA Digital Design Engineer - Sign-on Bonus
Nashua, New Hampshire, United States
OnsiteFull Time
6+ YOESecret-clearable engineer with 6+ years FPGA/ASIC experience, VHDL/Verilog RTL coding, timing closure, lab debug, familiarity with high-speed interfaces and revision control.
VHDL, Verilog, Xilinx Vivado, Intel/Altera Quartus, ChipScope, SignalTap, ILA, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, Matlab, Simulink, UVM, SystemVerilog, C, C++
1mo
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Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
2w
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Senior ASIC Hardware Design Engineer
Westford, Massachusetts, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in EE/CE/CS (or equivalent) with 5+ years industry experience; strong Verilog/SystemVerilog and RTL/microarchitecture experience; scripting in Perl or Python; understanding of physical implementation and VLSI.
Verilog, SystemVerilog, Perl, Python
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