2mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
6d
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Principal ASIC Design Engineer - Terawave
San Diego or Kent or Austin or California
$269k-$377k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOEBS/MS in Electrical Engineering or related,10+ years experience in complex SoC/ASIC design and verification,Verilog/System Verilog,ARM integration,DSP and high-speed interfaces,post-silicon bring-up experience.
Verilog, System Verilog, Matlab, SystemC, C, FPGA, AXI, PCIE, ARM
6d
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ASIC Verification Engineer
Irvine or San Jose
$101k-$162k/yr OnsiteFull Time
3+ YOEEngineering degree (Bachelors/Masters/PhD) with 3+ years verification experience (varies by degree), proficiency in HDL and verification, C/C++, scripting, strong communication and teamwork.
SystemVerilog UVM, SystemVerilog, Verilog, VHDL, C, C++, Python, PERL, TCL
3w
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ASIC/FPGA Verification Engineer (Experienced, Lead, or Senior)
El Segundo or Huntington Beach or Fairfax
$120k-$239k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or related field, 5+ years ASIC/FPGA verification experience, proficiency in SystemVerilog/UVM, OOP principles, coverage and code-coverage closure, waveform debug, revision control, and Linux.
UVM, SystemVerilog, SystemVerilog Assertions, svn, cvs, git, Linux, Palladium, Make, Perl, Python
2mo
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ASIC Design Engineer I, Satellite Communications
San Diego, California, United States
$123k-$170k/yr OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years in digital logic/DSP design; RTL implementation; DSP algorithms optimization.
MATLAB, RTL, UVM, SystemC, DPI-C, Verilog, VHDL
2mo
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Senior Principal Engineer Digital ASIC Design/Manager
San Diego, California, United States
$214k-$348k/yr OnsiteFull Time
15+ YOEBS or MS in Electrical Engineering; 15 years in Digital ASIC design; leadership; cross-functional collaboration; RTL/verification; experience with mixed-signal interfaces is a plus.
Verilog, SystemVerilog, LINT, LEC, RDC/CDC, SDF, Genus, Conformal, Innovus, Spyglass Lint, TetraMax, Xcelium, Cadence, Synopsys PrimeTime, VCS, UGV, UVM
3w
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ASIC/FPGA Verification Engineer (Experienced, Lead, or Senior)
El Segundo or Huntington Beach or Fairfax
$120k-$239k/yr OnsiteFull Time
5+ YOEBachelor's degree in engineering or related field, 5+ years ASIC/FPGA verification experience, proficiency with SystemVerilog/UVM, SV Assertions, revision control (svn/cvs/git), Linux, and waveform/debug tools; ability to obtain U.S. Secret clearance (U.S. citizenship required).
UVM, SystemVerilog, SystemVerilog Assertions, svn, cvs, git, Linux, Palladium, Make, Perl, Python, ARM, JESD204C, PCIe, Ethernet
3d
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ASIC Digital Design Engineer Lead
San Diego, California, United States
OnsiteFull Time
Senior-level engineering experience leading technical engagements with silicon suppliers to define, develop, and productize display digital designs across multifunctional teams.
2mo
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Principal Engineer, ASIC/VLSI Synthesis and Design
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
5+ YOE10-15 years in ASIC implementation and synthesis; strong RTL-to-GDSII flow; experience with UPF, ECOs, STA; 5-10 years on advanced nodes; scripting.
Fusion Compiler, Conformal ECO, Conformal Low Power, UPF, Scripting (Tcl, Python)
1mo
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Electrical Engineer, ASIC Program Lead-CA
San Diego, California, United States
$160k-$200k/yr OnsiteFull Time
12+ YOE12+ years experience with end-to-end custom ASIC/SoC development, mixed-signal and analog front-end expertise, strong digital design and verification experience, EE degree (BS required, MS preferred), lab debugging skills, and cross-functional collaboration.
Verilog, VHDL, SystemVerilog, UVM, EDA tools, Python, MATLAB, C/C++, Tcl, oscilloscopes, logic analyzers, spectrum analyzers, signal generators, precision measurement equipment, custom test fixtures
6d
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AI/ML driven ASIC Design and Implementation Automation Engineer
San Diego, California, United States
$148k-$203k/yr OnsiteFull Time
5+ YOE5+ years in AI/ML and software/CAD development, strong Python/C++ skills, experience with Unix/Linux and revision control, knowledge of VLSI design methodologies.
Python, C++, Unix/Linux, Git, BitBucket, DesignSync, MakeSplunk, Jenkins, LSF, CI/CD, System Verilog, Verilog, VHDL
3mo
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ASIC High Speed AMS Technical Leader
Carlsbad, California, United States
OnsiteFull Time
12+ YOELead analog/mixed-signal design for high-speed optical driver ICs; coordinate full-chip specs, design, verification; mentor engineers; collaborate across teams.
Cadence Virtuoso, Spectre, Caliber, SystemVerilog, Verilog-AMS, Python, C
3w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
2d
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
2w
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
1w
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Staff Systems Engineer
Carlsbad, California, United States
$134k-$175k/yr OnsiteFull Time
3+ YOEExperience validating ASICs for optical modules and data center applications, high-speed serial interfaces and re-timer design, signal integrity and DSP expertise, test automation, PCB/simulation (ADS, Cadence, Matlab), BS/MS/PhD with relevant years of experience.
ADS, Cadence, Matlab, PCIe, Ethernet, SerDes
1mo
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FPGA Verification Engineer, Air Vehicles
Costa Mesa, California, United States
$123k-$171k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog, UVM, SVA, industry simulators, Git, Linux; eligible to obtain U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, Python, Tcl, Makefile, SVUnit, Nix
1mo
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GPU Design Verification Engineer
San Diego, California, United States
$180k-$301k/yr OnsiteFull Time
10+ YOEMS/PhD or equivalent,10+ years ASIC design verification experience,SystemVerilog/UVM,constrained random,functional coverage,hw/sw co-simulation,emulation,strong debugging and GPU architecture knowledge.
SystemVerilog, UVM, emulation
3d
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Senior TPU Design Engineer, Silicon
Mountain View or San Diego
$163k-$236k/yr OnsiteFull Time
8+ YOE4+ MgmtBachelor's in EE/CE/CS or equivalent,8+ years RTL design with Verilog/System Verilog,4+ years leading IP/SoC teams,ARM/ASIC experience,EM/FPGA bring-up and strong communication.
Verilog, System Verilog, ARM, FPGA
3w
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FPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)
Costa Mesa, California, United States
RemoteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog/UVM/SVA, experience with industry simulators, Git and Linux, eligible for U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Nix
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