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44 asic engineer jobs at 12 companies in Gresham, OR

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Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBachelor's or Master's in EE/CS/CE (or equivalent), 5+ years ASIC verification experience, strong SystemVerilog and C/C++ skills, UVM, constrained-random and coverage-driven verification, familiarity with VCS/IES and debug tools.
SystemVerilog, C, C++, Universal Verification Methodology (UVM), VCS, IES, Debussy, GDB, Semiformal Verification (SFV), Perl, Python
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3mo
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ASIC Design Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
10+ YOEBS and 10+ years of relevant industry experience; Verilog RTL design experience.
Verilog, RTL, Synthesis, EDA, Front end tools
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Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOEBachelors/Masters in EE/CS/CE or equivalent, 5+ years verification experience, strong SystemVerilog and C/C++ skills, verification methodology experience (UVM, constrained-random, coverage, assertions), familiarity with VCS/IES and debug tools.
SystemVerilog, C, C++, VCS, IES, Debussy, GDB, Universal Verification Methodology (UVM), Semiformal Verification (SFV), Perl, Python
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Sr. Digital ASIC Engineer (Hillsboro, OR, US)
Hillsboro, Oregon, United States
$91k-$177k/yr OnsiteFull Time
Skyworks Solutions
Skyworks SolutionsNASDAQ: SWKS: Designs and manufactures analog and mixed-signal semiconductor solutions.
5+ YOEExperienced digital design engineer with RTL/Verilog/System Verilog skills, SOC/low-power design, MATLAB/Python/C modeling, FPGA prototyping, and silicon bring-up; typically 5+ years (BSEE) or 3+ (MSEE) industry experience.
Verilog, System Verilog, MATLAB, Python, C, Perl, Tcl, Makefiles, Shell scripts, FPGA, Oscilloscope, Logic Analyzer, Spectrum Analyzer
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2mo
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Electrical Engineer
Vancouver, Washington, United States
$93k-$144k/yr OnsiteFull Time
HP
HPNYSE: HPQ: Produces personal computers, printers, and related digital imaging products.
4+ YOEDesigns electrical hardware, FPGA/ASIC, Verilog/VHDL, debugging, testing, leadership of project teams.
FPGA, Verilog, VHDL, C++, Electrical Engineering
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3mo
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Hardware Design Engineer
Hillsboro, Oregon, United States
$107k-$199k/yr HybridFull Time
Rambus
RambusNASDAQ: RMBS: Develops high-performance memory interface chips and semiconductor IP.
5+ YOEStrong SystemVerilog/Verilog RTL design, ASIC/FPGA experience, RTL verification, scripting, 5+ years, BSEE.
SystemVerilog, Verilog, Questa, Incisive, VCS, Python, Perl, Tcl
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Principal Silicon Design Verification Engineer
Santa Clara or Mountain View or Hillsboro or Austin or Redmond
$143k-$275k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
3+ YOEDegree in EE/CE/CS (or equivalent) with 3+ to 8+ years technical engineering experience depending on degree, experience in ASIC/SoC verification, UVM/SystemVerilog/Verilog and C proficiency, ability to pass Microsoft security screening.
UVM, C, Verilog, System Verilog
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Integrated Circuit Design Verification Engineer
Vancouver, Washington, United States
$173k-$259k/yr OnsiteFull Time
Snap
SnapNYSE: SNAP: Provides visual messaging software and augmented reality wearable devices.
10+ YOE10+ years ASIC design verification experience; strong UVM/SystemVerilog skills; Siemens Questa; develop UVM/assertion testbenches, functional and code coverage, scripting/automation in Linux.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
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Senior Applications and Solutions Engineer - Foundry Services
Phoenix or Santa Clara or Hillsboro
$122k-$232k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
4+ YOEUS citizen; ability to obtain US government security clearance; 4+ years CMOS/low-power/multi-voltage domain; ASIC design and verification experience; scripting in Python/Perl/Tcl.
Cadence, Synopsys, UPF/CPF, VCLP, Conformal LP, Python, Perl, Tcl
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Field Applications Engineering
San Jose or Hillsboro
OnsiteFull Time
Lattice Semiconductor
Lattice SemiconductorNASDAQ: LSCC: Designs and manufactures programmable logic devices (FPGAs).
7+ YOE7+ years FPGA/ASIC design experience with VHDL/Verilog/SystemVerilog and tool experience (Radiant, Diamond, Quartus, Vivado); Bachelor's in Electrical Engineering; strong communication and presentation skills; customer-facing experience and periodic travel availability.
VHDL, Verilog, SystemVerilog, Radiant, Diamond, Quartus, Vivado
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1w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
Siemens
SiemensXETRA: SIE: Manufactures industrial automation, infrastructure, and energy technology systems.
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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Principal Engineer - Memory-Centric AI Compute Architect
Hillsboro, Oregon, United States
$192k-$288k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
6+ YOEMaster's/PhD preferred; 6+ years (PhD) / 7+ years (Master's) / 8+ years (Bachelor's) ASIC design/verification/validation/integration experience; knowledge of memory and compute architectures, AI models, and performance modeling; proficiency in C/C++/Python/Perl.
Phyton, C, C++, Perl, Python, HBM, DRAM
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FPGA Engineering Manager (Nextest, Tualatin, OR)
Tualatin, Oregon, United States
$171k-$274k/yr OnsiteFull Time
Teradyne
TeradyneNASDAQ: TER: Designs and manufactures automated test equipment and advanced robotics systems.
12+ YOE5+ MgmtB.S./M.S. in EE,12+ years digital ASIC/FPGA design,5+ years project lead,verilog/RTL,Cadence and static timing tools,PCIe/DDR/AXI/SERDES experience,excellent communication and presentation skills.
verilog, RTL, Cadence, Vivado, Quartus, UVM, Linux, Windows, PCIe, DDR3, DDR4, DDR5, AXI, Ethernet, SPI, SERDES, Lint, CDC, ATE
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