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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign engineer with strong Verilog/SystemVerilog, ASIC design, RTL timing and verification experience.
Verilog, SystemVerilog, RTL, EDA tools, Python, Perl
1mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
1d
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Senior ASIC Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
2+ YOE2+ years ASIC verification experience, UVM experience, ability to build UVM testbenches, knowledge of digital logic, SoC architecture, AMBA protocols, scripting, and verification strategy.
UVM, ARM, AMBA, AHB, AXI
3mo
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ASIC Design Engineer
Santa Clara or United States
OnsiteFull Time
3+ YOEBachelor's degree with 3+ years of ASIC design experience; memory subsystem and RTL knowledge beneficial.
RTL, HDL, DFI, DRAM, Memory subsystem, Performance simulators
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign ASICs using Verilog/SystemVerilog; strong digital design, timing, RTL, verification, and collaboration with cross-functional teams.
Verilog, SystemVerilog, EDA tools, Synthesis, Lint, Perl, Python
2mo
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ASIC Design Engineer lll
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
4+ YOEBachelor's in electrical engineering; 4+ years in ASIC/SoC design; strong Verilog/SystemVerilog; experience with EDA tools; good communication; Perl/Python a plus; AI tool experience a plus.
Verilog, SystemVerilog, EDA tools, Perl, Python
1w
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Senior ASIC Design Engineer
Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOE5+ years ASIC or SoC design experience; BS/MS in relevant engineering or equivalent; RTL design, logic synthesis, timing analysis, SOC integration experience; strong scripting/programming (Perl, Python, C++).
Perl, Python, C++
1w
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
1mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
3mo
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Sr. Staff ASIC Verification Engineer
Palo Alto, California, United States
$237k-$296k/yr OnsiteFull Time
10+ YOETypically 10+ years in ASIC design verification; BS/MS or PhD in Electrical or Computer Engineering; deep computer architecture; NoC; UPF/CPF; Systolic Arrays/NPUs; CNN/Transformer mapping; compilers/toolchains.
SystemVerilog, UVM, SVA, ISO 26262, FIA, Emulation, FPGA
1mo
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Sr. ASIC Verification Engineer
Sunnyvale or Munich
OnsiteFull Time
4+ YOE4+ years ASIC verification experience; expert in SystemVerilog/UVM, constraint-random and coverage-driven verification; experience with C/C++/SystemC, high-speed interfaces, scripting (Python/Perl/TCL/Shell), and post-silicon validation; BS required, MS preferred.
SystemVerilog, UVM, C, C++, SystemC, Python, Perl, TCL, Shell, ARM, RISC-V, PCIe, Ethernet, DDR, HBM, SerDes
3mo
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ASIC Validation Engineer
Bay Area, California, United States
$168k-$297k/yr RemoteFull Time
4+ YOEBachelor's in Electrical Engineering; 4+ years in silicon/hardware validation; lab experience; scripting (Python); cross-functional collaboration.
Python, lab equipment, oscilloscopes, logic analyzers, power supplies, SPI, I2C, JTAG, UART
1mo
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ASIC/FPGA Design Engineer III
Denver or Highlands Ranch or Sunnyvale or Cambridge
$101k-$201k/yr OnsiteFull Time
3+ YOEUS citizen able to obtain DoD Secret clearance, BS in Electrical Engineering (or equivalent), 3+ years professional FPGA development, HDL experience (VHDL/Verilog/SystemVerilog), and experience across ASIC/FPGA lifecycle.
VHDL, Verilog, SystemVerilog, Linux, AMD/Xilinx Vivado, Microchip Libero, Microsoft Project, JIRA, Earned Value Management System (EVMS)
1mo
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ASIC Formal Verification Engineer, TPU Compute
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical/Computer Engineering or Computer Science; 8 years in silicon/ASIC/SoC design; experience with SystemVerilog Assertions and formal verification.
1mo
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Principal Analog/Mixed-Signal ASIC Engineer
Sunnyvale, California, United States
$258k-$294k/yr HybridFull Time
10+ YOEPh.D. in EE or related field, 10+ years ASIC AMS and/or high-speed design experience, leading ASIC tape-outs, top-level ASIC architecture ownership, DRC/LVS/PI/SI verification experience, strong communication.
Register-Transfer Level (RTL), SOS, Git, Calibre
3mo
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SR ASIC SoC Design Engineer
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
Senior SoC/ASIC design engineer with experience in embedded subsystems, AI networking ASICs, chiplet-based SoCs, RTL design, and cross-functional collaboration.
SystemVerilog, Verilog, PCIe, NoCs, AMBA protocols (AXI/AHB/APB), CSR generation frameworks, RTL, Synthesis, Emulation, FPGA, SoC IP generation and configuration tools
3mo
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ASIC Architect
Santa Clara, California, United States
$192k-$287k/yr OnsiteFull Time
15+ YOE15+ years in Electrical/Computer Engineering with Masters or 10+ years with PhD; strong architecture leadership; experience with ASIC product architectures; knowledge of PCIe, CXL, UALink, Ethernet; ARM CPU subsystem; hardware/SoC co-design and security.
PCIe, CXL, Ethernet, UALink, Data Network Switching, ARM CPU Subsystem
3mo
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Lead ASIC/FPGA Design Engineer
Livermore, California, United States
OnsiteFull Time
5+ YOELead RTL design of high-speed ASIC/FPGA modem; strong DSP, FEC integration, and power/performance optimizations; requires security clearance.
Verilog, SystemVerilog, LINT, CDC, RDC, Test benche s, Synthesis, Power/Area analysis, STA, Place and Route
1mo
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ASIC Design Engineer (eInfochips)
Mountain View, California, United States
OnsiteFull Time
5+ YOE5+ years Verilog/SystemVerilog design; Fusion Compiler experience; scripting; PCIe and AXI interfaces; ARM Fabric IP; IPXACT; EDA tools.
Fusion Compiler, VCS, Questa CDC, Spyglass Lint, Design Compiler, Genus, UPF, Python, Tcl, Perl, Verilog, SystemVerilog, AXI, AMBA, IPXACT
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