1w
Save
Mark Applied
Hide
ASIC Engineer, Architecture
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's (or equivalent), 8+ years in ASIC/silicon engineering, 5+ years in performance modeling; proficiency in C++, Python, SystemC; experience with microarchitectural analysis for data center/AI workloads.
C++, Python, SystemC, SystemVerilog, VHDL
2w
Save
Mark Applied
Hide
ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
3mo
Save
Mark Applied
Hide
ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
1mo
Save
Mark Applied
Hide
Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
3w
Save
Mark Applied
Hide
Principal ASIC Design Engineer
Boulder or Austin
$180k-$220k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
10+ YOEMS/PhD in EE, 10+ years post-degree hardware experience, 2+ full ASIC design cycles, FPGA-to-ASIC experience, SystemVerilog/RTL proficiency, DSP RTL experience, knowledge of Cadence/Synopsys/Siemens EDA, mixed-signal background, mentoring experience.
RTL, SystemVerilog, Cadence, Synopsys, Siemens EDA, FPGA
1mo
Save
Mark Applied
Hide
Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
1mo
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineer
San Jose or Austin or Research Triangle Park
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree in Electrical or Computer Engineering with relevant ASIC experience (varies by degree), experience with EDA tools (Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus), STA experience, and Python scripting.
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, Tweaker, Static Timing Analysis (STA), Python, AI tools
1mo
Save
Mark Applied
Hide
Sr Principal ASIC Design Engineer - Terawave
San Diego or California or Austin or Texas or Kent
$308k-$431k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
15+ YOEExperienced ASIC/SoC design and verification engineer with expertise in Verilog/SystemVerilog, DSP structures, ARM integration, interface protocols, FPGA flows, post-silicon bring-up; BS/MS in EE or related and 15+ years experience required.
Verilog, SystemVerilog, MATLAB, SystemC, C
1mo
Save
Mark Applied
Hide
ASIC Design Verification Engineer
Austin, Texas, United States
HybridFull Time
Several years of RTL verification experience in IP/ASIC/SoC, deep SystemVerilog and UVM knowledge, testbench architecture, scripting (TCL/Python/Perl), Linux/GIT experience, and BS/MS in EE/CE or equivalent experience.
SystemVerilog, UVM, TLM, TCL, Python, Perl, Linux, GIT, LSF
1mo
Save
Mark Applied
Hide
ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
1w
Save
Mark Applied
Hide
Senior Staff ASIC CAD Flow Infrastructure Engineer
Austin, Texas, United States
$129k-$191k/yr OnsiteFull Time
5+ YOE5+ years ASIC CAD/EDA or infrastructure engineering experience, proficiency in Python, Tcl, Shell, Linux, experience supporting Synopsys/Cadence/Siemens EDA tools, strong ASIC/SoC design-flow knowledge, bachelor’s degree in CS/EE (advanced degree or equivalent experience acceptable).
Python, Tcl, Shell, Linux, Synopsys, Cadence, Siemens EDA, EDA
1mo
Save
Mark Applied
Hide
ASIC Design Verification Engineer
Austin, Texas, United States
$156k-$268k/yr OnsiteFull Time
Develop and execute IP verification architectures and test plans using System Verilog, UVM, SystemC, Verilog and C/C++; debug regressions, analyze coverage, and participate in code reviews. BS/MS in engineering or CS required. This role is not eligible for visa sponsorship.
System Verilog, UVM, SystemC, Verilog, C, C++, Linux, Windows, VIP
3mo
Save
Mark Applied
Hide
ASIC Design Engineer – Fabric/Interconnect
Austin, Texas, United States
OnsiteFull Time
3+ YOEBS in a relevant field with 3+ years of experience; knowledge of interconnect fabrics, RTL, and memory hierarchy; experience with synthesis, verification, and power/performance optimization.
RTL, Synthesis, Front-end tools
2mo
Save
Mark Applied
Hide
Senior ASIC Design Engineer
Austin or United States
RemoteFull Time
8+ YOE8+ years in digital design with Verilog/SystemVerilog; RTL design for high-speed data paths; Ethernet host adapters; timing closure; system-level debug; strong communication.
Verilog, SystemVerilog, EDA tools, timing analysis
2mo
Save
Mark Applied
Hide
ASIC RTL Design Engineer (784246)
Austin, Texas, United States
HybridFull Time
3+ YOEBS in Electrical or Computer Engineering; several years of hands-on RTL design experience; strong digital logic; proficient in C/C++, TCL, Python; SystemVerilog/Verilog/VHDL; CDC/STA knowledge; RTL linting/CDC tools; AMBA experience; EDA tool familiarity; Git/Linux.
SystemVerilog, Verilog, VHDL, C, C++, Python, TCL, EDA tools, SpyGlass, AMBA, Cadence, Mentor, Synopsys, Git, Linux
1mo
Save
Mark Applied
Hide
Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
3w
Save
Mark Applied
Hide
ASIC Design Verification Engineer (Santa Clara, CA)
Santa Clara or Austin
$127k-$190k/yr OnsiteFull Time
3+ YOE3+ years DV experience using UVM/assertion-based verification; experience verifying SoC/subsystems, caches, DDR, memory VIPs, DDR PHY, formal verification, PASIM, C++ and Python exposure; bachelor's/master's/PhD in science or engineering.
UVM, SystemVerilog, C++, Python, PASIM, UPF
3w
Save
Mark Applied
Hide
Senior Staff Application Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEMS in Engineering required, 10+ years in power management, experience with firmware-enabled products and large-scale ASIC/SoC power, multiphase DC/DC converters, mixed-signal ICs, control loop theory, FPGA prototyping, lab equipment and automation.
FPGA, ASIC, Network Analyzer, Oscilloscope, Waveform Generator
1mo
Save
Mark Applied
Hide
Staff Systems Engineer (Austin, TX, US)
Austin, Texas, United States
$114k-$220k/yr OnsiteFull Time
6+ YOEMSEE 6+ years or BSEE 8+ years with systems design; MATLAB; SystemVerilog, UVM, RNM; FPGA/ASIC design; lab equipment; RF/PLL knowledge.
MATLAB, SystemVerilog, UVM, RNM, FPGA, ASIC
2mo
Save
Mark Applied
Hide
Applications Engineering, Sr Engineer - 17248
Austin, Texas, United States
$95k-$142k/yr OnsiteFull Time
MS in engineering; hands-on with EDA tools; IC/ASIC flow knowledge; Python or Tcl; low power and reliability knowledge.
EDA tools, Python, Tcl, Spice, RTL to GDSII
Explore Jobs