81 asic engineer jobs at 21 companies in Paramount, CA
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Principal ASIC Engineer
El Segundo, California, United States
$211k-$285k/yr OnsiteFull Time
20+ YOEUS-person requirement for security clearance, BS in engineering or related field, ~20+ years ASIC/FPGA design & verification experience, SystemVerilog/UVM expertise, hardware integration and team leadership.
SystemVerilog, System Verilog Assertions, Palladium, UVM, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
1w
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
1w
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
2mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
1d
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Senior ASIC Emulation Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python/Perl/TCL), C/C++ firmware experience, and cross-functional debug skills.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C, C++, APB, AHB, AXI, JTAG, SPI, HAPS, Protium, PCIe, Ethernet, USB, SERDES
1w
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ASIC Verification Engineer
Irvine or San Jose
$101k-$162k/yr OnsiteFull Time
3+ YOEEngineering degree (Bachelors/Masters/PhD) with 3+ years verification experience (varies by degree), proficiency in HDL and verification, C/C++, scripting, strong communication and teamwork.
SystemVerilog UVM, SystemVerilog, Verilog, VHDL, C, C++, Python, PERL, TCL
1mo
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
1mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
2mo
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Electrical Engineer II ASIC/FPGA Verification (Onsite)
El Segundo, California, United States
$76k-$144k/yr OnsiteFull Time
2+ YOEDegree in STEM and at least 2 years of relevant experience; active SECRET security clearance; RTL/VHDL/Verilog experience; testbench development; familiarity with ASIC/FPGA verification.
SystemVerilog, OVM/UVM, VHDL, Verilog, Questasim, Synplify, Quartus, Vivado, C++, Perl, Git, Subversion
1mo
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Sr. ASIC Design Verification Engineer, Amazon Leo
Sunnyvale or San Diego or Los Angeles County
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/CE/EE, 7+ years verification experience (communications preferred), 5+ years with UVM and C/C++ and scripting, familiarity with Matlab and formal verification preferred; must meet U.S. export-control eligibility.
UVM, SystemC, DPI-C, Matlab, C/C++, FPGA
2mo
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
4d
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
1mo
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Hardware Engineer, Mid
El Segundo, California, United States
$62k-$141k/yr OnsiteFull Time
7+ YOE7+ years hardware engineering experience, bachelor’s in Electrical or Computer Engineering, Secret clearance, experience with avionics hardware reviews (PDR/CDR/TRR), requirements and verification development, risk management, and up to 10% travel.
VHDL, Verilog, embedded C, ASIC, FPGA, DO-254
1mo
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Electrical Engineer III/IV
Burbank, California, United States
$125k-$177k/yr OnsiteFull Time
8+ YOEBA/BS in engineering, 8+ years relevant experience, US Person required for ITAR work, expertise in analog/digital/micro-electronics, VHDL, ASIC, DO-254/DO-160, magnetics, switching power supplies, hardware/software integration, and strong communication skills.
VHDL, DO-254, DO-160, Kaizen, 5S, Lean
2w
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
1mo
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FPGA Verification Engineer, Air Vehicles
Costa Mesa, California, United States
$123k-$171k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog, UVM, SVA, industry simulators, Git, Linux; eligible to obtain U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, Python, Tcl, Makefile, SVUnit, Nix
1mo
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
3w
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Principal Electronics Design Engineer
Garden Grove, California, United States
$140k-$190k/yr OnsiteFull Time
10+ YOEBSEE and 10+ years electronic systems design experience, FPGA and embedded microprocessor design, GNSS/M-Code/SAASM, Ethernet/PTP, schematic capture, team leadership, ability to obtain secret clearance and U.S. citizenship.
FPGA, PWB, GNSS, M-Code, SAASM, Ethernet, Precision Time Protocol (PTP), SoC, SoM, ASIC
4w
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FPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)
Costa Mesa, California, United States
RemoteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog/UVM/SVA, experience with industry simulators, Git and Linux, eligible for U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Nix
5d
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Principal Design Validation & Test (DVT) Engineer
Irvine, California, United States
OnsiteFull Time
8+ YOE8+ years post-silicon validation/DVT experience with complex ASICs/SoCs; Bachelor's in EE/CE/CS or related; Python skills; lab equipment and high-speed protocol expertise; strong debug and communication skills.
JTAG, Python, oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, Ethernet traffic generators, power measurement equipment, PCIe, Ethernet, SerDes, CXL, SPI, I²C, MDIO, RTL
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