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36 asic engineer jobs at 6 companies in Redlands, CA

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ASIC Design Engineer
Irvine or Andover
$108k-$173k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
6+ YOEBachelor's in Electrical Engineering with 8+ years of related experience or Master's in Electrical Engineering with 6+ years of related experience; ASIC implementation, synthesis, DFT, floorplanning, place & route, clocking, power planning and analysis, timing closure, signal integrity, physical design checks.
EDA tools, Synthesis tools, Place and Route (P&R) tools, Floorplanning tools, Clocking/Timing analysis tools, Power analysis tools
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
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1mo
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
RTX
RTXNYSE: RTX: RTX provides advanced aerospace and defense systems and services.
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
InnoPhase
InnoPhase: Designing energy-efficient semiconductor solutions for 5G cellular networks.
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
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Principal Engineer Digital Design
Irvine or California or Dallas or Texas
$164k-$241k/yr HybridFull Time
Infineon Technologies
Infineon TechnologiesFrankfurt Stock Exchange: IFX: Designs and manufactures semiconductors for power and IoT systems.
12+ YOEBachelor's degree in EE/Computer Engineering, 12+ years RTL design experience (Verilog/System Verilog), DSP algorithm implementation, fixed-point math, MATLAB/C/C++, FPGA/ASIC experience, and familiarity with EDA tools (Synopsys Design Compiler, Cadence).
Verilog, System Verilog, HDL, MATLAB, Simulink, C, C++, Synopsys Design Compiler, Cadence
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