197 asic engineer jobs at 38 companies in Salado, TX
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
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ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
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Senior ASIC Verification Engineer (PCIe/CXL)
San Jose or San Diego or Austin or Longmont
$146k-$250k/yr HybridFull Time
Expertise in ASIC verification, Verilog, SystemVerilog, UVM testbenches, and Python or Perl scripting; experience with PCIe, CXL, NVMe, or Ethernet; bachelor's or master's degree in computer or electrical engineering.
FPGA, ASIC, UVM, Verilog, SystemVerilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
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ASIC Design Verification Engineer
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debug; scripting; and a bachelor's or master's degree in electrical or computer engineering preferred.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF
3w
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ASIC Digital Design Engineer Lead
Austin, Texas, United States
OnsiteFull Time
Senior engineering leader with strong ASIC/digital design background, supplier engagement, cross-functional communication, and schedule-driven delivery.
3w
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Senior ASIC Design Engineer – Clocks IP
Santa Clara or Austin
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical Engineering or equivalent, 3+ years relevant ASIC/RTL experience, Verilog and Python skills, strong knowledge of logic optimization and PPA trade-offs, excellent collaboration and communication.
Verilog, python
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ASIC DFT Engineer
San Jose or Austin
$165k-$241k/yr HybridFull Time
7+ YOEBachelor's or Master's in Electrical/Computer Engineering with 7+ years experience in DFT, ATPG, Jtag/scan/BIST, EDA tools (TestMax/Tetramax/Tessent/PrimeTime), gate-level simulation, and post-silicon validation.
Jtag, BIST, ATPG, TestMax, Tetramax, Tessent, PrimeTime, VCS, P1687, System Verilog, Verilog
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ASIC Design Verification Engineer (784248)
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debugging; scripting with TCL, Python, or Perl; and a bachelor's or master's degree in engineering or equivalent experience.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF, AMBA APB, AXI, ACE-Lite, CHI
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
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ASIC Digital Design Engineer (HPC IP)
Austin, Texas, United States
$114k-$170k/yr OnsiteFull Time
5+ YOEBSEE or MSEE and 5+ years in ASIC digital design and verification, with RTL expertise, EDA tools, interface protocols, analytical problem-solving, and cross-functional communication skills.
RTL, Electronic Design Automation (EDA), PCI Express (PCIe), Compute Express Link (CXL), DDR, Ethernet
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Senior Staff ASIC CAD Flow Infrastructure Engineer
Austin, Texas, United States
$129k-$191k/yr OnsiteFull Time
5+ YOE5+ years ASIC CAD/EDA or infrastructure engineering experience, proficiency in Python, Tcl, Shell, Linux, experience supporting Synopsys/Cadence/Siemens EDA tools, strong ASIC/SoC design-flow knowledge, bachelor’s degree in CS/EE (advanced degree or equivalent experience acceptable).
Python, Tcl, Shell, Linux, Synopsys, Cadence, Siemens EDA, EDA
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Senior ASIC Design Engineer - Terawave
San Diego or California or Austin or Kent or Texas or Washington
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in Electrical Engineering (or related), 8+ years experience in pre- and post-silicon SoC verification, strong SystemVerilog and DSP knowledge, emulation/FPGA/silicon bring-up experience, and verification methodology expertise.
SystemVerilog, MATLAB, SystemC, C, FPGA
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Senior ASIC Design Engineer
Austin or United States
RemoteFull Time
8+ YOE8+ years in digital design with Verilog/SystemVerilog; RTL design for high-speed data paths; Ethernet host adapters; timing closure; system-level debug; strong communication.
Verilog, SystemVerilog, EDA tools, timing analysis
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Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
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Senior Hardware Design Engineer
Austin or San Jose
$120k-$200k/yr OnsiteFull Time
3+ YOEMaster's in computer or electrical engineering with 3–5 years' experience, or bachelor's with 5–7 years. Requires SystemVerilog RTL, ASIC, digital design, PPA, synthesis, STA, CDC, LEC, SVA, Python, Linux shell, and Git.
SystemVerilog, SystemVerilog Assertions (SVA), AXI, PCIe, Ethernet, HBM, DDR, Git, Python, Linux shell, FPGA, ASIC, RTL, EDA
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Senior Staff Application Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEMS in Engineering required, 10+ years in power management, experience with firmware-enabled products and large-scale ASIC/SoC power, multiphase DC/DC converters, mixed-signal ICs, control loop theory, FPGA prototyping, lab equipment and automation.
FPGA, ASIC, Network Analyzer, Oscilloscope, Waveform Generator
3w
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Product Power Engineer
Santa Clara or Hsinchu or Austin or Bengaluru
$179k-$219k/yr OnsiteFull Time
3+ YOEMS/PhD in CS or Computer Architecture,3+ years power benchmarking/analysis experience,knowledge of architecture/logic/circuit power impacts,ASIC power analysis experience,and strong problem-solving skills.
RISC-V, RTL, FPGA, ASIC
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