91 fpga engineer jobs at 40 companies in Salado, TX
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Sr. FPGA Engineer
Singapore or Austin or Hsinchu or Shanghai or Shenzhen
OnsiteFull Time
8+ YOEBSEE/BSCE with 8+ years FPGA design and 6+ years SoC design experience. Experience with RTL/Verilog/System Verilog, FPGA bring-up, timing constraints, Xilinx Vivado/ISE, Intel Quartus Prime Pro, git, Python, and YAML.
Xilinx Vivado, ISE, Intel Quartus Prime Pro, Cadence, git, Python, YAML, Verilog, System Verilog, C, AMD VU19P, Stratix 10, AMD FPGA, Siemens proFPGA, ARM MPS4, I2C, I3C, MSPI, UART, USB
3w
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Lead FPGA Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBachelor’s degree in a related technical field and 5–10 years of FPGA or platform engineering experience. Requires FPGA design, RTL, verification, timing, lab debugging, and digital interface expertise.
FPGA, RTL, AMD/Xilinx, Intel/Altera, SPI, I2C, UART, Ethernet, PCIe, JESD, digital oscilloscopes, logic analyzers, function generators, printed circuit boards (PCBs)
3w
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System FPGA Engineer
Santa Clara or Austin
$152k-$228k/yr OnsiteFull Time
5+ YOEBachelor's or higher in engineering/CS and 5+ years FPGA implementation and verification experience; proficiency in Verilog/SystemVerilog, Python, cocotb, git/GitHub, vendor FPGA toolchains; strong communication skills.
Python, git, GitHub, cocotb, Verilog, SystemVerilog, AMD/Xilinx Vivado/Vitis, Intel/Altera Quartus Prime, JTAG, oscilloscope
3mo
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FPGA Engineer (TX, Austin)
Austin, Texas, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and systems; experience with RTL, C/C++, Python, VHDL/Verilog; FPGA toolchains; security clearance.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Altera, Stratix, AXI, ACE, Avalon, cocotb, pyuvm
3w
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FPGA Engineer Intern (Summer 2027 - Austin)
Austin or Chicago
OnsiteInternship
Student in Computer/Electrical Engineering (BS/MS/PhD) graduating Dec 2027–Jun 2028; hands-on FPGA/ASIC digital design experience; VHDL/Verilog/System Verilog experience; strong engineering instincts and teamwork skills.
FPGAs, ASICs, VHDL, Verilog, System Verilog
3w
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FPGA Engineer: Physical AI & Robotics
San Jose or Austin
HybridFull Time
Experienced FPGA/Adaptive SoC engineer with FPGA RTL and embedded software skills, familiarity with Verilog/SystemVerilog/VHDL, C/C++, Embedded Linux/Yocto, hardware debugging, and ability to work with customers on Physical AI solutions.
AMD Vivado, Vitis, Vitis HLS, Yocto, Verilog, SystemVerilog, VHDL, C, C++, PCIe, Ethernet, DisplayPort, MIPI CSI/DSI, USB, CAN, SPI, I2C, UART, GPIO, ROS 2, Git, JTAG, oscilloscope, protocol analyzer, logic analyzer
3w
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FPGA Design Engineer III
Austin, Texas, United States
OnsiteFull Time
3+ YOE3+ years Verilog RTL FPGA design experience, Bachelor's degree in EE/CE, full FPGA design flow knowledge, proficiency with major FPGA tool suites, and experience with verification and timing closure.
Verilog, VHDL, SystemVerilog, Microchip PolarFire SoC, RISC-V, PCIe, Ethernet, SERDES, UVM, Libero SoC, Xilinx Vivado, Intel Quartus, logic analyzers, oscilloscopes, Linux
4w
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Lead FPGA Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS,5+ years FPGA design experience, expertise in RTL, simulation/synthesis/timing, experience with AMD/Xilinx or Intel/Altera toolchains, familiarity with SPI,I2C,UART,Ethernet,PCIe,JESD and lab-based debug; leadership and cross-functional communication skills.
AMD/Xilinx, Intel/Altera, SPI, I2C, UART, Ethernet, PCIe, JESD, RTL, simulation, synthesis, timing analysis, digital oscilloscope, logic analyzer, function generator
2mo
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FPGA Engineer Engineer (eInfochips)
San Jose or Austin
OnsiteFull Time
9+ YOE9+ years experience; proficient in Verilog/System Verilog, EDA tools (VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus), IPXACT, UPF, PCIe/AXI/APB, ARM fabric; scripting with Python/Tcl/Perl; timing signoff and clock-crossing expertise.
Verilog, System Verilog, Python, Tcl, Perl, VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus, IPXACT, UPF
3mo
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Senior FPGA & Emulation Performance Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
5+ YOE5+ years in hardware emulation and FPGA environments, benchmarking and profiling skills, Linux and scripting (Python,Bash), scheduler integration, familiarity with Prometheus/Grafana and EDA vendor APIs.
Prometheus, Grafana, Linux, Python, Bash, Cadence, Synopsys, Siemens
1mo
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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Senior Principal Electrical Engineer - FPGA Development
Round Rock, Texas, United States
$174k-$226k/yr OnsiteFull Time
12+ YOE12+ years product development experience; advanced FPGA technologies, Verilog/SystemVerilog and HDL coding; RTL design and simulation; strong analog and digital fundamentals; hardware-software integration. Toolchain experience (Lattice/Xilinx/Altera, Synopsys VCS), Python and Git preferred.
Verilog, SystemVerilog, HDL, RTL, Lattice, Xilinx, Altera, Synopsys VCS, Python, Batch, Git
2w
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2027 Internship- Hardware Engineer (FPGA)
Austin or New York City
OnsiteInternship
Currently pursuing a Masters in Electrical Engineering; experience with SystemVerilog/Verilog, Python or C++, basic network protocols, strong problem solving and communication.
SystemVerilog, Verilog, Python, C++, HackerRank
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
2mo
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Electrical Engineer, Compute Architecture
Austin or South San Francisco
$105k-$176k/yr OnsiteFull Time
Bachelor’s in Electrical Engineering or related field; experience in electronics design, FPGA-based systems, timing & high-speed interfaces.
FPGA, Verilog, SystemVerilog, PCIe, MIPI, LVDS, JESD204, Ethernet, Altium
1mo
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Electrical Engineer
Austin, Texas, United States
$116k-$182k/yr OnsiteFull Time
7+ YOE7+ years electrical engineering experience; degree in electrical engineering or related field preferred; expertise in power optimization, hardware design, FPGA, PCB, C++, Python, MATLAB; leadership of project teams and product development.
C++, MATLAB, Python, Field-Programmable Gate Array (FPGA), Oscilloscope, Schematic Capture
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Electrical Engineer
Austin, Texas, United States
$116k-$182k/yr OnsiteFull Time
7+ YOE7+ years electrical design experience; leads project teams; four-year or graduate degree in electrical engineering preferred; skills in C++, Python, MATLAB, FPGA, PCB design, schematic capture, and debugging.
C++, MATLAB, Python (Programming Language), Oscilloscope, Field-Programmable Gate Array (FPGA), Printed Circuit Board, Schematic Capture
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Electrical Engineer
Austin, Texas, United States
$116k-$182k/yr OnsiteFull Time
7+ YOELead multiple electrical hardware project teams; 7+ years electrical/hardware design experience preferred; recommended Bachelors/Masters in electrical engineering or related; expertise in power optimization, FPGA, PCB, C++, Python, MATLAB.
C++, Python, MATLAB, Oscilloscope, Field-Programmable Gate Array (FPGA), Printed Circuit Board, Schematic Capture
1d
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Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
2mo
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Hardware Digital Engineer (PCB Design)
Austin, Texas, United States
HybridFull Time
5+ YOEBachelor's in Electrical, Computer, or Software Engineering; 5+ years digital hardware design; VHDL/SystemVerilog; FPGA; schematic capture; PCB layout; relocation to Austin; US work authorization without sponsorship.
VHDL, SystemVerilog, Schematic Capture, PCB Design Tools, FPGA
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