290 design verification engineer jobs at 67 companies in Hercules, CA
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
1mo
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
1d
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Staff Design Verification Engineer
Sunnyvale, California, United States
$250k-$300k/yr OnsiteFull Time
10+ YOERequires 10+ years of design verification experience, SystemVerilog, DPI, UVM, Python or Perl, scalable testbench development, verification tools, and strong debugging skills. BS or MS in computer science or electrical engineering desired.
SystemVerilog, DPI, UVM, Python, Perl
4w
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
4w
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
1w
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Design Verification Engineer
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
3+ YOERequires 3–5 years of experience with VLSI hardware verification, SystemVerilog, UVM, AMBA protocols, test planning, coverage analysis, simulation debugging, regressions, and power-aware verification.
SystemVerilog, UVM, AMBA, UPF, CPF, VLSI, HVL
4w
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Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
1w
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ASIC Design Verification Engineer
Santa Clara, California, United States
$107k-$161k/yr OnsiteFull Time
0.5+ YOEBachelor's degree in science or engineering; experience with architecture/design tools, scripting/programming, and design verification methods preferred; works under supervision and communicates technical information.
RTL to GDS Flow, Virtuoso
1w
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Design Verification Engineer
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
3+ YOERequires 3–5 years of VLSI hardware verification experience, strong SystemVerilog and UVM knowledge, AMBA protocol understanding, debugging, coverage analysis, and simulation experience.
SystemVerilog, UVM, AMBA, UPF, CPF, VLSI, HVL
1mo
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Design Verification Engineer
Santa Clara, California, United States
$142k-$200k/yr HybridFull Time
3+ YOEBS/MS in EE/CS (3+ years DV), hands-on coding in SystemVerilog, C, C++, Python, experience with UVM/ABV and simulation/formal verification, familiarity with interconnect protocols and AI-assisted development tools.
SystemVerilog, C, C++, Python, UVM, ABV, JasperGold, VC Formal, AI-assisted development tools, emulation, FPGA
3w
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOEDevelop and execute verification plans using SystemVerilog/UVM and emulation platforms; 5+ years verification experience; bachelor\u0002s in EE/CE/CS; strong debugging, scripting, and coverage skills.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal
1mo
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
3w
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOE5+ years verification experience, Bachelor in EE/CE/CS, strong SystemVerilog/UVM skills, emulation platform experience, scripting (Python/Perl/TCL), debug and coverage-driven verification expertise.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal, UPF, CPF, FPGA
2mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
1mo
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CPU Design Verification Engineer
Mountain View, California, United States
$138k-$198k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CE/CS (or equivalent), 3+ years verification experience with UVM/SystemVerilog, B.S. required; preferred MS/PhD, low-power verification, scripting (Python/Perl/Shell/Bash), ARM ISA, and Linux/Android knowledge.
Universal Verification Methodology (UVM), SystemVerilog, Python, Perl, Shell, Bash, Advanced RISC Machine (ARM), Linux, Android
2mo
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Design Verification Engineer, Principal
Santa Clara, California, United States
$159k-$238k/yr OnsiteFull Time
5+ YOEBS in CE/EE/CS with 10+ years (or MS/PhD with 5+ years) verification and firmware/software experience; expertise in System Verilog, UVM, random verification, Python/Perl, EDA tools, OOD, Linux, C++ and ARM assembly; leadership and tape-out experience.
System Verilog, UVM, Python, Perl, EDA Verification tools, Linux, C++, ARM assembly
1mo
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Design Verification Engineer (Silicon Engineering)
Palo Alto, California, United States
$135k-$210k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS/CompE,1+ years design verification experience, SystemVerilog/UVM, Python/MATLAB scripting, testbench and coverage development, RTL and pre/post-silicon validation experience.
SystemVerilog, UVM, Python, MATLAB
3w
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOEBachelor's in EE/CE/CS,5+ years verification experience,proficient in SystemVerilog and UVM,experience with emulation platforms (Palladium/ZeBu/Veloce),debugging,and scripting (Python/Perl/TCL).
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal, FPGA
3w
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Design Verification Senior Staff Engineer
Irvine or Santa Clara
$136k-$201k/yr OnsiteFull Time
5+ YOEBachelor's degree in EE/Computer Engineering, 5+ years ASIC/SoC verification experience, strong SystemVerilog/UVM and protocol knowledge, scripting (Python/Perl/Shell), debug and coverage skills.
System Verilog, UVM, Python, Perl, Shell, Palladium, Veloce
1d
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Sr. FPGA Design & Verification Engineer
San Francisco, California, United States
$137k-$188k/yr HybridFull Time
2+ YOEMaster's degree plus 2+ years or bachelor's degree plus 3+ years of engineering experience; expertise in FPGA and RTL design, VHDL, Verilog, SystemVerilog, simulation, verification, debugging, laboratory equipment, and scripting.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers
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