2mo
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ASIC Verification Engineer
Santa Clara, California, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS or MS in EE/CS/CE; 2+ years verification; strong verification methodology experience; C++ and/or SystemVerilog; UVM; tools: VCS, Debussy, GDB; strong communication.
C++, SystemVerilog, VCS, Debussy, GDB, UVM, verification methodologies
2mo
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
3mo
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Formal Verification Engineer
Austin or Beaverton or Cupertino
OnsiteFull Time
0+ YOEBachelor's degree in electrical or computer engineering with 0 years of experience; strong Verification knowledge preferred.
1mo
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Design Verification Engineer
Santa Clara, California, United States
$146k-$250k/yr OnsiteFull Time
SystemVerilog/UVM verification expertise; IP/subsystem/SoC verification; testbench development; strong debugging and collaboration.
SystemVerilog, UVM, VCS, Verdi/DVE, Python, Shell, Tcl, Make
1w
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
16h
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
10+ YOE10+ years verification experience, strong UVM/SystemVerilog/Verilog/Python/C/C++ skills, experience with constrained-random stimulus, coverage, assertions, and EDA tools; BS/MS in EE/CE/CS or equivalent experience.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi, Debussy, GDB, HLS
2mo
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Physical Verification Engineer
Phoenix or Santa Clara or Hillsboro
$129k-$245k/yr HybridFull Time
3+ YOEUS citizenship, ability to obtain US government security clearance, Bachelor in Electrical/Computer Engineering or STEM, 3+ years in CMOS processes and layout verification, 3+ years in parasitic extraction and scripting
Python, Perl, Tcl, Shell, StarRC, Quantus, xACT, ICV, Calibre, Pegasus, LVS, DRC, ERC, PERC, Parasitic Extraction Tools
1mo
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Staff Engineer, Design Verification
Santa Clara, California, United States
$114k-$171k/yr OnsiteFull Time
3+ YOEBachelor's in Computer/Electrical Engineering + 3+ years (2+ with MS/PhD); System Verilog/UVM, verification test-plan development, verification tools, C/C++, Python/Perl, and Linux proficiency.
System Verilog/UVM, C/C++, Python, Perl, Linux, CXL, PCIE, Ethernet, ARM
1mo
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Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
6d
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Verification CAD Engineer
Milpitas, California, United States
$160k-$265k/yr HybridFull Time
7+ YOEB.S./M.S. in EE/CE/CS,7+ years design verification experience,expert SystemVerilog/UVM and SVA/CDV,advanced Python and Shell skills,Linux and regression farm experience (LSF/NC/Slurm),familiarity with Cadence verification tools.
SystemVerilog, UVM, SVA, Python, Shell, Perl, Xcelium, SimVision, vManager, Verissium, Linux, LSF, NC, Slurm
1w
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Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
2w
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Systems Verification Engineer I
Fremont, California, United States
$106k-$132k/yr OnsiteFull Time
0+ YOEBS in Science/Engineering/Math, 0–2 years product development/verification experience for medical devices or IVD, writing requirements, multidisciplinary engineering knowledge, flow cytometry familiarity, experience with system engineering tools.
Helix ALM, Jira, JMP, TestRail, DOORs, SpectroFlo
1mo
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Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
3mo
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Design Verification Engineer - APS
Santa Clara, California, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; UVM, Verilog, SystemVerilog, Python experience; mixed-signal verification; scalable testbenches; team mentoring.
UVM, Verilog, SystemVerilog, Python, EDA tools
3mo
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FPGA Verification Engineer - Avionics
Saratoga, California, United States
$150k-$250k/yr OnsiteFull Time
4+ YOE4+ years FPGA/ASIC verification; SystemVerilog/UVM; develop verification environments; RTL simulation; functional coverage; timing analysis.
SystemVerilog, UVM, RTL simulators, VCS, QuestaSim, Python, TCL, lint, CDC analysis tools
1mo
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Design Verification Engineer
Sunnyvale, California, United States
$190k-$230k/yr OnsiteFull Time
3+ YOE3+ years design verification experience; deep knowledge of SystemVerilog, DPI, UVM; strong programming (object-oriented) skills; experience with testbenches, simulation, emulation, and silicon bring-up.
SystemVerilog, DPI, UVM, Python, Perl
1mo
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Performance Verification Engineer
Mountain View, California, United States
$200k-$350k/yr OnsiteFull Time
8+ YOEMaster's degree plus ~8 years experience in performance validation/verification of complex SoCs, performance modeling, debugging and correlation, tool-flow ownership, and collaboration with RTL designers and architects.
1d
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Digital Verification Engineer
Santa Clara, California, United States
OnsiteFull Time
3+ YOE3+ years digital verification experience for FPGA/ASIC, proficiency in Verilog/SystemVerilog, experience with Modelsim/Questasim or NC-Verilog, BS/MS in EE/CE, strong coverage and assertion skills.
Verilog, SystemVerilog, Modelsim, Questasim, NC-Verilog, UVM
2w
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
2d
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOEDevelop and execute verification plans using SystemVerilog/UVM and emulation platforms; 5+ years verification experience; bachelor\u0002s in EE/CE/CS; strong debugging, scripting, and coverage skills.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal
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