52 design verification engineer jobs at 29 companies in Wildomar, CA
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
1w
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
6d
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Design Verification Engineer
Rancho Bernardo or San Diego
$81k-$142k/yr OnsiteFull Time
4+ YOEBachelor's, master's, or PhD in engineering or related technical field, with 4+ years' experience for bachelor's or 2+ for master's; ASME standards, PDM, drawing interpretation, communication, and analytical skills.
Product Data Management (PDM), ASME Y14.100-2017, ASME Y14.5-2018, GD&T
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
3w
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Design Verification Senior Staff Engineer
Irvine or Santa Clara
$136k-$201k/yr OnsiteFull Time
5+ YOEBachelor's degree in EE/Computer Engineering, 5+ years ASIC/SoC verification experience, strong SystemVerilog/UVM and protocol knowledge, scripting (Python/Perl/Shell), debug and coverage skills.
System Verilog, UVM, Python, Perl, Shell, Palladium, Veloce
2mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
1d
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Staff Design Verification Test Engineer
Costa Mesa, California, United States
$191k-$253k/yr OnsiteFull Time
12+ YOEBachelor's degree in engineering, physics, or related field; 12+ years in test, verification, or product engineering; RF/microwave measurement, DVT, NPI, failure triage, and engineering leadership experience.
Lattice OS, spectrum analyzers, signal analyzers, VNAs, signal generators, power meters
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
1mo
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship and ability to obtain U.S. Secret clearance; BS in engineering or related field; experience with ASIC/FPGA design or verification and HDL (Verilog/VHDL/System Verilog); familiarity with verification methodologies and scripting.
Verilog, VHDL, System Verilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
3mo
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Sr. Satellite Design Verification Engineer, Amazon Leo
Irvine or Austin or Sunnyvale or Redmond or San Diego
OnsiteFull Time
7+ YOEBachelor's in Electrical/Communications Engineering; 3+ years UVM/SystemC/DPI-C; 7+ years verification in communications; preferred advanced degree; Matlab familiarity; DV/integration experience.
UVM, C, SystemC, DPI-C, Matlab
6h
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RFIC design engineer
Irvine, California, United States
OnsiteFull Time
Requires advanced understanding of RFIC design, simulation, layout, and verification; deep submicron process experience; industrial experience; and a Ph.D. or Master of Science in Electrical Engineering.
1mo
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
1mo
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
1mo
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RFIC - PLL Design Engineer
Irvine, California, United States
OnsiteFull Time
Design and validate RFIC phase-locked loops (PLLs) and radio transceivers for wireless SoCs; collaborate across RF/analog, systems, VLSI, verification, test, and firmware/software teams.
1mo
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
2mo
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Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
5+ YOEBachelor's/Master's in EE, 5+ years full-chip physical verification experience, multiple tapeouts, hands-on with ICV or Calibre, ability to assemble PV flow and floorplanning expertise; Tcl/Python/shell automation preferred.
ICV, Calibre, Tcl, Python, Shell
1mo
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Design Quality Engineer
Irvine, California, United States
$105k-$135k/yr OnsiteFull Time
5+ YOEBS in technical or life science,5+ years in medical device quality systems (ISO 13485,21 CFR 820),strong technical writing,test planning,verification/validation experience,MS Office proficiency,and ability to travel up to 90 days/yr.
Microsoft Office
2mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
4w
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Senior Design Quality Engineer - Medical Devices
Carlsbad or Chicago or Raleigh or Durham or Greensboro or Pittsboro
$100k-$140k/yr HybridFull Time
5+ YOEBachelor's degree,5+ years relevant experience,knowledge of FDA 21 CFR 820/ISO 13485/ISO 14971,cGMP,GxP; experience with electromechanical devices, audits, risk management, and verification/validation.
1mo
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Director of Verification & Validation
Huntington Beach, California, United States
$180k-$230k/yr OnsiteFull Time
8+ YOEBachelor's in Biomedical or Mechanical Engineering, 8+ years Class III medical device V&V, knowledge of FDA and IEC/ISO standards, design control expertise, strong technical writing, and experience leading V&V teams.
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