1mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
2mo
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Design Verification Engineer - Early Career
Santa Clara or Irvine
$87k-$130k/yr OnsiteFull Time
1+ YOEBachelor’s or Master’s in Electrical/Computer Engineering with 1–3 years experience; Verilog/VHDL; Linux and Python; PCB/architecture knowledge; experience with UVM and ASIC verification.
Verilog, VHDL, UVM, Synopsys, Cadence, Mentor Graphics, Linux, Python, PCIe, Memory Architecture
4d
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Senior Verification Engineer
Arlington or Seal Beach
$146k-$234k/yr OnsiteFull Time
7+ YOELead and execute software and system-level testing, develop test plans and automated scripts, verify integrated system behavior, track defects, and support release readiness; requires extensive software testing and technical leadership experience.
Selenium, Cypress, Jira, Jenkins, Gitlab, Ansible, Amazon Web Services (AWS), Kubernetes, Docker, Postgres, MySQL, Linux
1mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
1mo
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FPGA Verification Engineer, Air Vehicles
Costa Mesa, California, United States
$123k-$171k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog, UVM, SVA, industry simulators, Git, Linux; eligible to obtain U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, Python, Tcl, Makefile, SVUnit, Nix
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
6d
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Senior Software Verification & Validation Engineer
Irvine, California, United States
OnsiteFull Time
3+ YOEBachelor's in a technical discipline, 3+ years embedded software V&V or system testing, experience with requirements-based verification, Python scripting, test documentation, and cross-functional collaboration.
Python, JIRA, Azure DevOps, Polarion, Jama, Windows, Microsoft Word, Microsoft Excel, Microsoft PowerPoint, Microsoft Outlook, multimeter, oscilloscope, function generator, logic analyzer
3mo
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Lead Verification & Validation Engineer
Palo Alto or Irvine
$130k-$155k/yr OnsiteFull Time
5+ YOELead V&V strategy, mentor engineers, design/test automation, and oversee automotive software/system validation.
CAN, LIN, Ethernet, FlexRay, dSPACE, Vector VT, DBC, LDF, ARXML, HIL, MATLAB, Python, C/C++, Automotive testing tools
2mo
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Sr. Satellite Design Verification Engineer, Amazon Leo
Irvine or Austin or Sunnyvale or Redmond or San Diego
OnsiteFull Time
7+ YOEBachelor's in Electrical/Communications Engineering; 3+ years UVM/SystemC/DPI-C; 7+ years verification in communications; preferred advanced degree; Matlab familiarity; DV/integration experience.
UVM, C, SystemC, DPI-C, Matlab
2d
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V and V Engineer System Verification Engineer
Irvine, California, United States
$120k-$130k/yr OnsiteFull Time
10+ YOE9+ years system/software testing in aerospace with embedded testing, scripting for automation, avionics standards (DO-178b/ARP-4754A), experience with A429/CAN and tools like DOORS, SVN or MKS; Bachelor's in computer science required.
DOORS, SVN, MKS, A429, CAN, DO-178b
2mo
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ASIC/FPGA Verification Engineer - (Associate, Experienced, or Lead) - SoCal
El Segundo or Huntington Beach
$86k-$171k/yr OnsiteFull Time
Bachelor's in engineering or related field; experience in ASIC/FPGA verification; SystemVerilog/UVM; Linux; testbenches; code coverage; waveform tools; SVN/Git.
SystemVerilog, UVM, SystemVerilog Assertions, Linux, Python, Make, Perl, Git, SVN, Waveform tools, Palladium, JESD204C, PCIe
1mo
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
2mo
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ASIC/FPGA Verification Engineer - (Associate, Experienced, or Lead) - SoCal
El Segundo or Huntington Beach
OnsiteFull Time
5+ YOEBachelor's degree in engineering or related field; experience in ASIC/FPGA verification; SystemVerilog/UVM; HDL proficiency; testbenches, coverage models, and regression testing experience.
SystemVerilog, UVM, HDL, Verilog, Python, Make, Perl, Git, SV Assertions
1mo
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
6d
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Senior Software Verification & Validation Engineer
Irvine, California, United States
$88k-$147k/yr OnsiteFull Time
3+ YOEBachelor's in engineering or CS,3+ years embedded/software V&V experience,requirements-based testing,Python automation,defect tracking tools (JIRA,Azure DevOps,Polarion,Jama),Windows and Microsoft Office proficiency.
Python, JIRA, Azure DevOps, Polarion, Jama, Windows, Microsoft Word, Microsoft Excel, Microsoft PowerPoint, Microsoft Outlook, multimeter, oscilloscope, function generator, logic analyzer
1w
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Senior/Principal Full-Chip Physical Verification Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
7+ YOE7+ years full-chip physical verification experience, BS in Electrical Engineering (MS preferred), hands-on with ICV or Calibre, DRC/ERC analysis, tapeout experience, floorplanning expertise; Tcl/Python/shell scripting preferred.
ICV, Calibre, Tcl, Python, shell
1mo
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Wireless SOC Verification Engineer
Irvine, California, United States
OnsiteFull Time
Experience verifying complex SoCs using UVM testbenches, developing coverage-driven and directed tests, deploying AI tools, and collaborating across product teams to improve tape-out readiness.
UVM
2w
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FPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)
Costa Mesa, California, United States
RemoteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog/UVM/SVA, experience with industry simulators, Git and Linux, eligible for U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Nix
2mo
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Software Engineer, Verification and Validation (Perception)
Irvine, California, United States
$135k-$190k/yr OnsiteFull Time
3+ YOE3+ years in verification/validation for robotics; experience with LiDAR, cameras, GPS, and IMUs; develop test plans, validation criteria, and metrics; strong cross-functional communication.
LiDAR, Cameras, GPS, IMUs
1w
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ASIC/FPGA Verification Engineer - (Associate, Experienced, or Lead) - SoCal
El Segundo or Huntington Beach
$86k-$171k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent, ASIC/FPGA verification experience using SystemVerilog/UVM, coverage and regression development, testbench design, revision control (svn/cvs/git), and Linux proficiency.
UVM, SystemVerilog, SystemVerilog Assertions, svn, cvs, git, Linux, Palladium, Make, Perl, Python, JESD204C, PCIe, Ethernet
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