65 dft jobs at 24 companies in Round Rock, TX
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DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT experience including specification, architecture, insertion and analysis; silicon bring-up/debug/validation of DFT features; fault modeling; ATPG/MBIST/JTAG/ATE experience; strong problem-solving and communication skills.
Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, TestKompress, ATPG, MBIST, JTAG, ATE
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DFT Engineer
Austin, Texas, United States
$129k-$207k/yr OnsiteFull Time
8+ YOEBSEE with 12+ years or MSEE with 8+ years, strong DFT knowledge including MBIST, scan insertion, ATPG, silicon bring-up and yield improvement, Mentor Tessent/Synopsys experience, and Perl scripting.
Mentor Tessent, Synopsys, Perl
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Principal DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT implementation and verification experience including scan architectures, JTAG, memory MBIST, ATPG; Verilog/VHDL RTL knowledge; ability to handle RTL DFT changes, analyze ATPG/DRC reports, and support test pattern bring-up.
RTL, MBIST, ATPG, JTAG, TAP, ATE, Verilog, VHDL, SDF
2mo
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Semicustom DFT Strategy Lead
Austin, Texas, United States
HybridFull Time
Senior DFT and testing leader with cross-functional collaboration, roadmap development, and experience with EDA/ATE tools.
EDA tools, ATE tools, CAD tools, DFT tools, Internal DFT tools
2w
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DFT Implementation Engineer
Austin, Texas, United States
$142k-$200k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years DFT/SoC design experience, RTL design (Verilog/VHDL/SystemVerilog), ATPG/scan/MBIST experience, Tessent and industry DFT tool knowledge, scripting (TCL/Perl/Python).
Tessent Shell, SSN, Tessent Fast IO, ISTK, Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, Cadence Modus, ATPG, MBIST, Verilog, VHDL, SystemVerilog, TCL, Perl, Python, UPF
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Sr. Staff Engineer - DFT
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS/MS in ECE/EE with 10+ years DFT experience; skilled in scan, scan compression, boundary scan, MBIST, low-power DFT, ATPG and RTL; experience with Tessent MBIST flow, Cadence Genus/Modus, and scripting (Tcl, Perl, Python).
Cadence Genus, Modus, Tessent, Tcl, Perl, Python
1mo
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DFT Technical Leader
San Jose or Austin or New York City or New York or Washington or United States or Canada
$184k-$264k/yr HybridFull Time
10+ YOEBachelor's or Master's in Electrical/Computer Engineering, 10+ years experience in DFT, Jtag/Scan/BIST, ATPG and EDA tools, gate-level simulation and post-silicon validation experience.
Jtag, Scan, BIST, ATPG, TestMax, Tetramax, Tessent, PrimeTime, VCS, P1687, Verilog, System Verilog
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
6d
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Principal DFT Engineer (Silicon Engineering)
Irvine or Austin or Palo Alto
$210k-$340k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE/CS,10+ years ASIC and DFT experience including scan insertion, ATPG, and post-silicon validation; strong RTL, debugging, and scripting skills.
Siemens Tessent, Perl, Python, Tcl, C+, Verilog, SystemVerilog, UPF, SDF, DRC, ATE
1w
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Senior Principal DFT Design Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOE10+ years SoC/ASIC digital design experience with strong DFT expertise including scan insertion, compression scan, MBIST/LBIST, and ATPG; Verilog knowledge and strong debugging and collaboration skills.
Verilog, ATPG, MBIST, LBIST, JTAG 1149.1/6, IEEE1500, IEEE1687, Cadence
3w
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DFT CAD Engineer
Austin, Texas, United States
OnsiteFull Time
Collaborate on development of upcoming hardware products and address novel engineering challenges.
3mo
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Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Austin, Texas, United States
$159k-$215k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design; DFT, ATPG, JTAG, MBIST; scripting; collaboration with PD/architecture; RTL through silicon experience.
ATPG, JTAG, MBIST, RTL, Python, Perl, Tcl, DFT/SCAN/ATPG tools
1w
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Test Engineer
San Jose or Austin or Pittsburgh or Tucson
$150k-$190k/yr OnsiteFull Time
5+ YOE5+ years fabless or IDM semiconductor test experience, hands-on DFT, ATPG/MBIST/JTAG, ATE bringup on Advantest or Teradyne, OSAT coordination, yield analysis, and strong communication skills.
DFT, ATPG, MBIST, JTAG, STIL, PDL, SVF, Advantest, Teradyne, Python, Perl, VCD, RTL
1mo
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Principal SLT Test Engineer
Austin, Texas, United States
OnsiteFull Time
Proven functional/ATE test engineering background, experience with SLT, DFT and production test, scripting skills (Python, TCL, Perl, Shell), degree in electronics or related field, ability to lead and mentor engineers.
SLT, ATE, DFT, JTAG, BIST, MBIST, Python, TCL, Perl, Shell
3w
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Coherent Fabric Design
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
Experienced RTL logic designer with fabric/interconnect knowledge, SystemVerilog, AMBA CHI/AXI familiarity, PCIe/Ethernet/DDR exposure, lint/synthesis/STA/DFT experience, scripting and Unix proficiency, and a relevant engineering degree.
SystemVerilog, AMBA CHI, AXI, PCI Express (PCIe), Ethernet, DDR, Lint, Synthesis, Static timing analysis, DFT, Perl, Ruby, Unix, Makefiles
1w
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Electrical Senior Principal Engineer
Round Rock, Texas, United States
$174k-$226k/yr OnsiteFull Time
12+ YOE12+ years experience delivering complex electronics from concept to production; strong debugging with oscilloscopes, logic analyzers and power instrumentation; fluency with EMI/EMC, DFM/DFT; excellent communication.
oscilloscope, logic analyzer, power instrumentation, lab instrumentation
1w
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Infrastructure and Tools Developer (787687)
Austin, Texas, United States
HybridFull Time
Hands-on experience with ASIC/SoC design, RTL, Verilog, UVM/SystemVerilog, front-end EDA tools, synthesis/STA/DFT, and scripting (Perl, Python, bash, csh). Strong communication and presentation skills.
Verilog, UVM, SystemVerilog, Perl, Python, bash, csh, CloudBees Jenkins, Load Sharing Facility (LSF), Slurm, Altair
1mo
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Senior ASIC Floorplan Design Engineer
Santa Clara or Austin
$196k-$311k/yr OnsiteFull Time
10+ YOEMSEE/MSCE or equivalent experience, 10+ years in chip development, expertise in SOC/CPU/graphics floorplanning and physical design, experience with power/clock/DFT/place-and-route/timing, and programming in Python/Perl/C++.
Python, Perl, C++
1w
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Infrastructure and Tools Developer
Austin, Texas, United States
OnsiteFull Time
Several years of ASIC/SoC frontend experience with RTL/Verilog/SystemVerilog,UVM; scripting in Perl/Python/bash/csh; familiarity with synthesis, STA, DFT and front-end verification tools; BS/MS in EE/CS.
Verilog, UVM, SystemVerilog, Perl, Python, bash, csh, CloudBees Jenkins, LSF (Load Sharing Facility), Slurm, Altair
3mo
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Engineering Manager, Digital & Mixed-Signal Hardware
Austin, Texas, United States
OnsiteFull Time
8+ YOE2+ MgmtLead digital and mixed-signal hardware teams; oversee architecture, design reviews, staffing, and process maturity in aerospace/defense; 7-9 years experience; BS or higher in Electrical or Computer Engineering; SI/DFM/DFT expertise; leadership experience.
Altium, Xilinx Vivado, Ansys SiWave, ADS SiPro
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