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85 digital design engineer jobs at 47 companies in Georgetown, TX

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Senior Digital Design Engineer
Rochester or Austin or Herndon
$105k-$231k/yr OnsiteFull Time
CACI International
CACI InternationalNYSE: CACI: Provides information technology and engineering services for government agencies.
10+ YOEBachelor's in electrical engineering or related, 10+ years digital electronics and PCB design experience, knowledge of high-speed interfaces, lab test equipment, and engineering review processes. U.S. citizenship and ability to obtain clearance required.
Siemens PADS, VHDL, Verilog, Logic Analyzers, Signal Generators, Oscilloscopes, Protocol Analyzers, Spectrum Analyzers, Network Analyzers, USB3.x, Ethernet, PCIe, I2C, SPI
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Digital Layout Design Engineer
Austin, Texas, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Design custom digital layouts for ASICs, create digital macros and libraries, and collaborate with integration, CAD, circuit, and technology engineers.
CAD
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Senior Digital Design Engineer
Rochester or Austin or Herndon
$105k-$231k/yr OnsiteFull Time
CACI
CACINYSE: CACI: Provides information technology and professional services to government clients.
10+ YOEBachelor's in EE,10+ years digital electronics design experience, PCB and high-speed digital expertise, proficiency with interfaces/protocols, lab test equipment experience, strong communication skills; U.S. citizenship required.
Siemens PADS, VHDL, Verilog, USB3.x, Ethernet, PCIe, I2C, SPI, Logic Analyzer, Signal Generator, Oscilloscope, Protocol Analyzer, Spectrum Analyzer, Network Analyzer
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBachelors or Master's in EE/CE or equivalent experience, 5+ years relevant experience, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), delivering high-bandwidth datapath blocks, deep ASIC design flow knowledge.
NVLink Fusion, NVLink, PCI-Express, Ethernet, UCIE, RTL, SoC
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Senior Digital Design Engineer
Austin, Texas, United States
OnsiteFull Time
NXP Semiconductors
NXP SemiconductorsNASDAQ: NXPI: Designs and manufactures semiconductors for automotive and IoT applications.
4+ YOEBachelors in EE/CE/CS required, 4+ years IP or SoC design experience, expert Verilog, knowledge of SoC architecture, experience with Lint/CDC/STA, ARM AMBA desired; C and scripting (Perl/Python) and functional safety are a plus.
Verilog, System Verilog, Lint, CDC, Static Timing Analysis (STA), ARM AMBA, C, Perl, Python
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
Silicon Labs
Silicon LabsNASDAQ: SLAB: Designs and manufactures semiconductors and wireless connectivity solutions.
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
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Hardware Digital Engineer (PCB Design)
Austin, Texas, United States
HybridFull Time
Emerson
EmersonNYSE: EMR: Engineering industrial automation and software solutions for global industries.
5+ YOEBachelor's in Electrical, Computer, or Software Engineering; 5+ years digital hardware design; VHDL/SystemVerilog; FPGA; schematic capture; PCB layout; relocation to Austin; US work authorization without sponsorship.
VHDL, SystemVerilog, Schematic Capture, PCB Design Tools, FPGA
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
Silicon Labs
Silicon LabsNASDAQ: SLAB: Designs and manufactures wireless semiconductors and software for IoT.
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
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Sr. Staff Engineer - Digital Design Verification
Austin, Texas, United States
OnsiteFull Time
Ambiq
AmbiqNYSE: AMBQ: Develops energy-efficient semiconductors for edge AI devices.
8+ YOEBSEE or MSEE with 8+ years verifying complex SoC digital designs using SystemVerilog/UVM and C/C++; proven tape-outs, SoC-level verification, and strong collaboration and debugging skills.
SystemVerilog, UVM, Verilog, C/C++, Python, Perl, Makefile
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Digital Design Verification, Principal Engineer-17853
Austin, Texas, United States
$166k-$249k/yr OnsiteFull Time
Synopsys
SynopsysNasdaq: SNPS: Provides software and IP for semiconductor design and manufacturing.
12+ YOE12+ years IP/SoC verification experience, proficiency with Synopsys verification tools, agentic AI exposure, scripting in SystemVerilog/UVM/Tcl/Python, and BS/MS in electrical/electronics/computer engineering.
VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), VIPs, Cursor, Microsoft VS Code co-pilot, SystemVerilog, UVM, Tcl, Python
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
Olix
Olix: Developing optical hardware for artificial intelligence inference.
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
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Senior Design Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
Arm
ArmNASDAQ: ARM: Designs and licenses processor architectures and semiconductor intellectual property.
7+ YOEBachelors/Masters in CS/ECE,7+ years designing complex SoC/compute subsystems,strong digital hardware design and Verilog experience,PCIe/DDR/HBM/UCIe integration,RTL development and SoC design methodologies.
Verilog, Perl, Python, SystemVerilog, UVM, OVM, PCIe, DDR, HBM, UCIe, Ethernet
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DFT Design Engineer
Austin or San Jose
OnsiteFull Time
Cadence Design Systems
Cadence Design SystemsNASDAQ: CDNS: Develops computational software and hardware for electronic system design.
3+ YOE3-12 years SoC/ASIC digital design experience with focus on DFT, scan insertion, compression scan, MBIST, ATPG, EMR not required. US citizenship preferred.
Cadence, Verilog, ATPG, MBIST, JTAG 1149.1, JTAG 1149.6, IEEE1500, IEEE1687
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2mo
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Digital Modem Engineer
Austin or Chicago or New York City or London
$150k-$250k/yr OnsiteFull Time
Jump Trading
Jump Trading: Global proprietary trading firm specializing in algorithmic and high-frequency strategies
5+ YOE5+ years in digital modem design, modeling, and implementation; strong FPGA/ASIC knowledge; Python/C/C++/Matlab; MS/PhD in EE/CS or equivalent.
Python, C++, C, Matlab
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CPU Physical Design Engineer
Austin, Texas, United States
$106k-$200k/yr OnsiteFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
2+ YOEBachelor’s or Master’s in Computer/Electrical Engineering with relevant experience; strong background in digital synthesis, physical design flows, and verification.
Synopsys, Cadence, Synthesis, Place and Route, Static Timing Analysis, DRC/LVS, TCL scripting
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VLSI Design Engineer
Austin, Texas, United States
OnsiteFull Time
Retym
Retym: Developing coherent DSP silicon for AI data center infrastructure.
5+ YOE5+ years ASIC/VLSI digital design experience; strong Verilog/SystemVerilog; familiarity with simulation and verification methodologies, synthesis/timing analysis, and protocol implementation; BS/MS in EE/CE.
Verilog, SystemVerilog, Python, Perl, TCL, EDA tools, SDC, CDC, Linting, Formal Verification
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VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
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3mo
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Senior ASIC Design Engineer
Austin or United States
RemoteFull Time
Cornelis Networks
Cornelis Networks: High-performance networking solutions for AI and HPC datacenters.
8+ YOE8+ years in digital design with Verilog/SystemVerilog; RTL design for high-speed data paths; Ethernet host adapters; timing closure; system-level debug; strong communication.
Verilog, SystemVerilog, EDA tools, timing analysis
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Senior Staff Systems Design Engineer
Austin, Texas, United States
HybridFull Time
Mythic
Mythic: Develops energy-efficient analog processors for AI inference.
7+ YOEHardware board-level design, high-speed digital design, PCB design and bring-up, with vendor collaboration and DFM focus.
Altium, Cadence, PCB design tools
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