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270 digital design engineer jobs at 91 companies in Tracy, CA

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Digital Design Engineer
Saratoga, California, United States
$150k-$250k/yr OnsiteFull Time
E-Space
E-Space: Builds sustainable LEO satellite networks for global IoT connectivity
Design digital avionics boards, high-speed interfaces, clocking, power budgeting, radiation-tolerant design; collaborate with FPGA teams; board bring-up and design reviews.
Altium Designer, HyperLynx SI, HyperLynx PI, Full-Wave, SPICE-based circuit simulation, FPGA vendor toolchains
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Digital Design Engineer
San Jose, California, United States
$130k-$200k/yr OnsiteFull Time
Credo Semiconductor
Credo SemiconductorNASDAQ: CRDO: Designing high-speed semiconductor connectivity solutions for data infrastructure.
5+ YOEBS/MS/PhD in EE/CE,5+ years digital RTL design experience,SystemVerilog proficiency,ASIC flow and EDA tool experience,high-speed SerDes/DSP knowledge,Python/MATLAB/C++ familiarity.
System Verilog, Synopsys, Cadence, Siemens, Python, MATLAB, C++
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
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4w
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
Unconventional
Unconventional: Developing novel computing hardware for efficient AI acceleration.
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
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Principal Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
Astera Labs
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
5+ YOEBachelor’s or Master’s in Electrical/Computer Engineering or related field; 5-10 years in digital design for high-speed DSP data paths; SystemVerilog coding; experience with Synthesis, Lint, CDC, PrimeTime; RTL delivery; full design cycle; timing/area/power optimization; silicon issue resolution
SystemVerilog, EDA tools, Synthesis, Lint, CDC, PrimeTime
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Machine Learning Digital Design Engineer
Sunnyvale, California, United States
$178k-$250k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
8+ YOEBachelor's degree or equivalent, 8+ years hardware design experience for production silicon, expertise in digital µarchitecture, RTL coding, micro-architecture development, and cross-functional technical communication.
RTL, SoC, ASIC, DSP, microcontrollers
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Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
10+ YOE10+ years in digital/ASIC design with chip/design lead ownership; SystemVerilog RTL; synthesis/timing tools; cross-team integration leadership.
SystemVerilog, DC, Genus, PrimeTime, Tempus
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
Texas Instruments
Texas InstrumentsNASDAQ: TXN: Designs and manufactures semiconductors and integrated circuits.
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
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Technical Staff Engineer - Digital Design
San Jose, California, United States
$70k-$143k/yr HybridFull Time
Microchip Technology
Microchip TechnologyNASDAQ: MCHP: Designs and manufactures microcontrollers and mixed-signal semiconductor solutions.
12+ YOEBachelor's in EE/CE, 12+ years relevant experience (10+ in FPGA/ASIC IP and system design), VHDL/Verilog expertise, FPGA design/verification experience, strong digital design and architecture knowledge, excellent communication; US citizenship or permanent residency required.
VHDL, Verilog, Libero, Quartus, Vivado, Identify Debugger, SignalTap, ChipScope, ModelSim, QuestaSim, Python, TCL
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Digital Design Engineer - New College Grad
San Jose, California, United States
$99k-$183k/yr HybridFull Time
Rambus
RambusNASDAQ: RMBS: Develops high-performance memory interface chips and semiconductor IP.
Master's degree in EE or related field; experience with RTL coding, Verilog models, and analog/digital design; test support and chip bring-up; strong communication and team skills.
Verilog, RTL, Simulations, I2C, SPI, AHB, APB, Bench testing, ATE testing
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
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Principal Digital Design Engineer
San Jose, California, United States
$190k-$240k/yr HybridFull Time
Renesas Electronics
Renesas ElectronicsTokyo Stock Exchange: 6723: Designs and manufactures semiconductors for automotive and industrial systems.
8+ YOEMS/PhD EE with 8+ years or BS EE with 12+ years; SOC architecture experience, bus/interface protocols, embedded memory knowledge, RTL/DFT/synthesis flow, silicon bring-up, strong communication and team skills.
AHB, APB, AXI, USB, I2C, I3C, SPI, UART, SRAM, OTP, MTP, EE/Flash, DDR DRAM, Flash
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Senior Principal Engineer, Digital IC Design
Santa Clara, California, United States
$182k-$273k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
10+ YOEMSEE with 10+ years; proficient in digital logic, ASIC verification flows, Verilog/SystemVerilog/Vera/SystemC, Perl/Tcl, UNIX shells; strong communication; SerDes IP design/verification experience.
Verilog, SystemVerilog, Vera, SystemC, Perl, Tcl, UNIX Shell, MATLAB
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
Synopsys
SynopsysNasdaq: SNPS: Provides software and IP for semiconductor design and manufacturing.
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
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Distinguished Engineer, Digital IC Design
Santa Clara, California, United States
$210k-$314k/yr OnsiteFull Time
Marvell Technology
Marvell TechnologyNASDAQ: MRVL: Developing semiconductor solutions for cloud, enterprise, and AI infrastructure.
15+ YOEMaster's required (Ph.D. preferred),15+ years experience in uLED/uVCSEL, ASIC architecture, chiplet and multi-die design, demonstrated leadership, patents/publications, system integration expertise.
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SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
TikTok
TikTok: Global short-form video hosting and social media platform.
1+ YOEBachelor's in EE/CS or related, 1+ years front-end digital design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile).
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA, FPGA, ASIC
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Sr. Electrical Design Engineer (PCBA, analog/digital circuit design)
Milpitas, California, United States
OnsiteFull Time
KLA
KLANASDAQ: KLAC: Provides process control and yield management for semiconductor manufacturing.
3+ YOESenior engineer for analog/digital PCB design, with CAD tools experience, traveling up to 10%.
OrCAD, PSpice, LTspice, FPGA, Oscilloscope, Lab equipment
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
InnoPhase IoT
InnoPhase IoT: Develops ultra-low power wireless semiconductor platforms for IoT devices.
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
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