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691 verification engineer jobs at 126 companies in Tracy, CA

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ASIC Verification Engineer
Santa Clara, California, United States
$116k-$190k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
2+ YOEBS or MS in EE/CS/CE; 2+ years verification; strong verification methodology experience; C++ and/or SystemVerilog; UVM; tools: VCS, Debussy, GDB; strong communication.
C++, SystemVerilog, VCS, Debussy, GDB, UVM, verification methodologies
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
Lumilens
Lumilens: Designs photonic interconnects for AI supercomputing infrastructure.
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
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Formal Verification Engineer
Austin or Beaverton or Cupertino
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
0+ YOEBachelor's degree in electrical or computer engineering with 0 years of experience; strong Verification knowledge preferred.
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
MatX
MatX: Developing custom silicon chips optimized for large language models.
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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Physical Verification Engineer
Phoenix or Santa Clara or Hillsboro
$129k-$245k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
3+ YOEUS citizenship, ability to obtain US government security clearance, Bachelor in Electrical/Computer Engineering or STEM, 3+ years in CMOS processes and layout verification, 3+ years in parasitic extraction and scripting
Python, Perl, Tcl, Shell, StarRC, Quantus, xACT, ICV, Calibre, Pegasus, LVS, DRC, ERC, PERC, Parasitic Extraction Tools
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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Alpha Design AI
Alpha Design AI: AI-native EDA platform for semiconductor design and verification.
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
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Staff Engineer, Design Verification
Santa Clara, California, United States
$114k-$171k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
3+ YOEBachelor's in Computer/Electrical Engineering + 3+ years (2+ with MS/PhD); System Verilog/UVM, verification test-plan development, verification tools, C/C++, Python/Perl, and Linux proficiency.
System Verilog/UVM, C/C++, Python, Perl, Linux, CXL, PCIE, Ethernet, ARM
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Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Semiconductor foundry providing chip design and fabrication services.
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
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ASIC Verification Engineer
Santa Clara, California, United States
$116k-$219k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
2+ YOEBachelor's or Master's in EE/CS/CE (or equivalent), 2+ years verification experience, proficiency with SystemVerilog and/or C++, verification methodologies (UVM), simulation/debug tools (VCS, Debussy, GDB), strong debugging and communication skills.
C++, SystemVerilog, VCS, Debussy, GDB, UVM
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
Axiado
Axiado: Creates AI-driven security processors for data center infrastructure.
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
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Verification CAD Engineer
Milpitas, California, United States
$160k-$265k/yr HybridFull Time
Sandisk
SandiskNasdaq: SNDK: Designs and manufactures flash memory and data storage products.
7+ YOEB.S./M.S. in EE/CE/CS,7+ years design verification experience,expert SystemVerilog/UVM and SVA/CDV,advanced Python and Shell skills,Linux and regression farm experience (LSF/NC/Slurm),familiarity with Cadence verification tools.
SystemVerilog, UVM, SVA, Python, Shell, Perl, Xcelium, SimVision, vManager, Verissium, Linux, LSF, NC, Slurm
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Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
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Systems Verification Engineer I
Fremont, California, United States
$106k-$132k/yr OnsiteFull Time
Cytek Biosciences
Cytek BiosciencesNASDAQ: CTKB: Manufacturer of spectral flow cytometry instruments and biological reagents.
0+ YOEBS in Science/Engineering/Math, 0–2 years product development/verification experience for medical devices or IVD, writing requirements, multidisciplinary engineering knowledge, flow cytometry familiarity, experience with system engineering tools.
Helix ALM, Jira, JMP, TestRail, DOORs, SpectroFlo
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Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Manufacturer of semiconductors and provider of wafer fabrication services.
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
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Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Etched
Etched: Designs specialized AI chips optimized for transformer architectures.
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
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Design Verification Engineer - APS
Santa Clara, California, United States
OnsiteFull Time
Texas Instruments
Texas InstrumentsNASDAQ: TXN: Designs and manufactures semiconductors and integrated circuits.
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; UVM, Verilog, SystemVerilog, Python experience; mixed-signal verification; scalable testbenches; team mentoring.
UVM, Verilog, SystemVerilog, Python, EDA tools
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FPGA Verification Engineer - Avionics
Saratoga, California, United States
$150k-$250k/yr OnsiteFull Time
E-Space
E-Space: Builds sustainable LEO satellite networks for global IoT connectivity
4+ YOE4+ years FPGA/ASIC verification; SystemVerilog/UVM; develop verification environments; RTL simulation; functional coverage; timing analysis.
SystemVerilog, UVM, RTL simulators, VCS, QuestaSim, Python, TCL, lint, CDC analysis tools
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