2w
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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
3mo
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RTL Design Engineer
Cupertino or United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience in RTL design, Verilog/SystemVerilog, DSP concepts, and circuit verification.
Verilog, SystemVerilog, linting tools, clock-domain crossing checkers, Synthesis, Static Timing Analysis, Design-for-Test, Scripting (Perl, Python), Formal verification, DSP concepts, hardware optimization
1mo
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CPU Systems RTL Engineer
Santa Clara, California, United States
$167k-$251k/yr OnsiteFull Time
5+ YOEMS in Computer/Electrical Engineering with 5+ years CPU RTL experience; strong microarchitecture knowledge; Verilog or VHDL experience; familiarity with timing, power, and simulators; scripting with Perl or Python.
Verilog, VHDL, Perl, Python
1mo
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RTL Design Engineer
Mountain View, California, United States
$100k-$180k/yr OnsiteFull Time
8+ YOE8+ years VLSI/RTL design experience with System Verilog/Verilog, Python RTL generators, HLS, SoC integration, UPF low-power flow, synthesis/timing closure, linting and CDC/RDC checks, and emulation on Zebu/HAPS.
System Verilog, Verilog, Python, High-Level Synthesis (HLS), Zebu, HAPS, Unified Power Format (UPF)
1w
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RTL Design Engineer
San Jose, California, United States
HybridFull Time
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
1mo
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RTL Design Engineer, TPU Compute
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
4+ YOEBachelor's degree in EE/CE/CS or related field; 4 years digital design with SystemVerilog RTL; experience with computer architecture.
SystemVerilog, RTL, ASIC design, computer architecture, verification
1mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
2w
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
1mo
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
1mo
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
1mo
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Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
3mo
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Senior RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$159k-$194k/yr OnsiteFull Time
3+ YOE3+ years of RTL design experience; Verilog/SystemVerilog/VHDL; CPU RTL design; Chisel/Scala experience a plus; strong software engineering skills.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, Jira, Confluence
3mo
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RTL Design / Microarchitecture Engineer
Sunnyvale, California, United States
$160k-$220k/yr OnsiteFull Time
5+ YOE5–10 years of RTL design and microarchitecture experience; strong SystemVerilog/Verilog expertise; ASIC/SoC development experience.
SystemVerilog, Verilog, Synopsys VCS, Cadence Xcelium, Synopsys Design Compiler, Scripting (Python/TCL)
2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
5d
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
1mo
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
2mo
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
1d
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Senior Memory Controller RTL Design Engineer
Redmond or Mountain View or Raleigh or Austin or Hillsboro
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years experience depending on degree, strong Verilog/SystemVerilog RTL design skills, DDR4/DDR5 controller experience preferred, scripting (Perl/Tcl/Python), familiarity with front-end verification and low-power/timing checks, ability to pass Microsoft security and export control screenings.
Verilog, System Verilog, Perl, Tcl, Python
1mo
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
1mo
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Senior Principal Engineer, Micro-architecture and RTL
Santa Clara, California, United States
$182k-$273k/yr OnsiteFull Time
15+ YOEBachelor's in CS/EE with 15+ yrs; MS with 10-12 yrs; PhD with 8-10 yrs. SystemVerilog RTL, UVM, Ethernet, PCIe, CXL experience; leadership ability.
SystemVerilog, SystemVerilog Assertions, Universal Verification Methodology, RTL, PCIe, CXL, Ethernet
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