278 verification engineer jobs at 55 companies in Salado, TX
6d
Save
Mark Applied
Hide
Principal Verification Engineer
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOERequires a degree in electrical engineering, computer engineering, computer science, or related field and 3–8+ years of technical engineering experience depending on degree; verification, UVM, RTL, simulation, scripting, and security screening required.
Universal Verification Methodology (UVM), C, Zsh, Bash, Python, Perl, Verilog, Microsoft Azure, AXI, AMBA
1w
Save
Mark Applied
Hide
Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
2mo
Save
Mark Applied
Hide
Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
3mo
Save
Mark Applied
Hide
Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
1w
Save
Mark Applied
Hide
Digital Verification Engineer
Austin, Texas, United States
$125k/yr OnsiteFull Time
Master’s degree in electrical, electronics, or computer engineering; knowledge of digital design, Verilog, SystemVerilog, formal verification, Python or C/C++, SQL, Jenkins, Informatica, and debugging.
Verilog, SystemVerilog, Python, C, C++, SQL, Jenkins, Informatica, UVM
2mo
Save
Mark Applied
Hide
ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
1d
Save
Mark Applied
Hide
CPU Verification Engineer
Austin or Santa Clara
OnsiteFull Time
Requires a BS in electrical or computer engineering or equivalent experience, strong communication and teamwork, and verification expertise across CPU/SoC architecture, C/C++/assembly, UVM, SystemVerilog, Verilog, coverage, and assertions.
C, C++, UVM, SystemVerilog, Verilog
3mo
Save
Mark Applied
Hide
ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical/Computer Engineering or equivalent, 2+ years verification experience, SystemVerilog/UVM, Perl or Python scripting, experience with synthesis/simulation and debug tools, strong debugging and collaboration skills.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
4w
Save
Mark Applied
Hide
CPU Verification Engineer
Austin, Texas, United States
$106k-$200k/yr HybridFull Time
3+ YOEDegree in EE/CE or related STEM plus 2–3+ years verification experience; expertise in SystemVerilog/UVM, scripting (Python/Perl), C++, CPU architecture knowledge, debugging and verification methodologies.
SystemVerilog, UVM, Python, Perl, C++, VCS, GIT, Assembly
2w
Save
Mark Applied
Hide
Associate Staff Verification Engineer - Wireless
Austin, Texas, United States
$126k-$234k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering, 3–8 years of experience, and expertise in SV-UVM, C, verification, automation, SystemVerilog assertions, coverage, UPF, and real-number modeling.
UVM, C, MATLAB, Electronic Design Automation (EDA), SystemVerilog, SystemVerilog Assertion, UPF, Real Number Modeling (RNM), SPICE
1d
Save
Mark Applied
Hide
Senior SoC Verification Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
Verification engineers solve complex problems using machine learning, simulation software, model checking, and hardware prototyping systems; specific qualifications are not stated.
2w
Save
Mark Applied
Hide
Associate Staff Verification Engineer - Wireless
Austin, Texas, United States
$126k-$234k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering; 3–8 years' experience; SV-UVM, C, scripting, automation, verification, SystemVerilog assertions, coverage, UPF, and real-number modeling skills.
UVM, C, MATLAB, SystemVerilog, SystemVerilog Assertion, UPF, Spice
1w
Save
Mark Applied
Hide
Verification Engineer - New College Grad 2026
Santa Clara or Westford or Austin
$100k-$190k/yr OnsiteFull Time
Bachelor's or master's degree in electrical or computer engineering, C++ and SystemVerilog experience, scripting, verification methodologies, testbench architecture, debugging, and analytical and communication skills.
C++, SystemVerilog, VCS, Debussy, GDB
1mo
Save
Mark Applied
Hide
ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
3mo
Save
Mark Applied
Hide
Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
2mo
Save
Mark Applied
Hide
Principal Digital Verification Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEMasters in Electrical/Computer Engineering with 8+ years or Bachelor's with 10+ years experience; experience in DDR5/DDR6 verification and UVM.
UVM, SystemVerilog, DDR5/DDR6, verification environments, testbench
3mo
Save
Mark Applied
Hide
IP Verification Engineer
Austin, Texas, United States
HybridFull Time
Several years of industry RTL verification experience, strong SystemVerilog/UVM skills, RTL testbench and TLM modeling, HW emulation experience, scripting (TCL/Python/Perl), familiarity with SerDes/PCIe/ARM/DSP/Ethernet and AMBA protocols, and BS/MS in EE/CE.
SystemVerilog, UVM, TLM, SerDes, PCIe, ARM, DSP, Ethernet, TCL, Python, Perl, C, Assembly, Linux, GIT, LSF, AMBA, APB, AXI, ACE-Lite, CHI
2mo
Save
Mark Applied
Hide
Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
4w
Save
Mark Applied
Hide
ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
3mo
Save
Mark Applied
Hide
Design Verification Engineer (Einfochips)
Austin or San Jose
OnsiteFull Time
6+ YOE6+ years in System Verilog HVL and C/C++, 6+ years in UVM; strong testbench development, debug, and verification closure; experience with DSP, scripting, and version control tools.
SystemVerilog, HVL, C, C++, UVM, SVTB, Make, Perl, Python, Bugzilla, Subversion
Explore Jobs