186 design verification engineer jobs at 46 companies in Salado, TX
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
2mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
1mo
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Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
1mo
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
1mo
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Design Verification Engineer -Staff
Austin, Texas, United States
$154k-$231k/yr OnsiteFull Time
2+ YOEDegree in electrical/computer engineering or computer science and minimum 2 years experience in software/electrical/systems engineering with microprocessor design experience.
3mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
2mo
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Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Verify high-throughput cellular baseband modems and transceiver link controllers; strong problem solving and technical aptitude for complex engineering challenges.
1mo
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Design Verification Engineer (Silicon Engineering)
Austin, Texas, United States
OnsiteFull Time
1+ YOEBachelor's in EE/CS/CE,1+ years design verification experience,SystemVerilog/UVM and testbench development,Python/MATLAB scripting,ability to meet U.S. ITAR eligibility.
SystemVerilog, UVM, Python, MATLAB
3mo
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Design Verification Engineer (Einfochips)
Austin or San Jose
OnsiteFull Time
6+ YOE6+ years in System Verilog HVL and C/C++, 6+ years in UVM; strong testbench development, debug, and verification closure; experience with DSP, scripting, and version control tools.
SystemVerilog, HVL, C, C++, UVM, SVTB, Make, Perl, Python, Bugzilla, Subversion
2w
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ASIC Design Verification Engineer
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debug; scripting; and a bachelor's or master's degree in electrical or computer engineering preferred.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF
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Senior CPU Design Verification Engineer
Austin or Phoenix
$122k-$232k/yr HybridFull Time
4+ YOEBachelor's in electrical, computer, or related engineering plus 4+ years' experience, or master's plus 2+ years. Requires SystemVerilog, UVM, EDA tools, and pre-silicon CPU, SoC, or complex IP verification.
SystemVerilog, UVM, Electronic Design Automation (EDA), C, C++, Linux, Python, Perl
2w
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ASIC Design Verification Engineer (784248)
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debugging; scripting with TCL, Python, or Perl; and a bachelor's or master's degree in engineering or equivalent experience.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF, AMBA APB, AXI, ACE-Lite, CHI
2mo
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Digital Design Verification, Principal Engineer-17853
Austin, Texas, United States
$166k-$249k/yr OnsiteFull Time
12+ YOE12+ years IP/SoC verification experience, proficiency with Synopsys verification tools, agentic AI exposure, scripting in SystemVerilog/UVM/Tcl/Python, and BS/MS in electrical/electronics/computer engineering.
VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), VIPs, Cursor, Microsoft VS Code co-pilot, SystemVerilog, UVM, Tcl, Python
3w
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Staff Design Verification Engineer – High Performance CPU Core
Austin or Santa Clara
OnsiteFull Time
7+ YOE7+ years ASIC/CPU/SoC design verification experience, strong SystemVerilog and UVM skills, CPU microarchitecture knowledge, BS in EE/CE/CS, strong debug and verification strategy abilities.
SystemVerilog, UVM, Python, C, C++
6d
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Staff GPU Design Verification Engineer – Formal Verification
Austin, Texas, United States
$151k-$227k/yr OnsiteFull Time
5+ YOERequires 6+ years with a bachelor's, 4+ with a master's, or 2+ with a Ph.D.; 5+ years in GPU, CPU, or semiconductor formal verification; SystemVerilog, SVA, programming, architecture, and formal EDA expertise.
Python, Perl, C, C++, SystemVerilog, SystemVerilog Assertions (SVA), UVM (IEEE 1800 Universal Verification Methodology), Confluence, JIRA, UPF
3mo
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Satellite Design Verification Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or San Diego
$136k-$184k/yr OnsiteFull Time
5+ YOE2+ years UVM, C, SystemC, and scripting; 5+ years verification for communication systems; Bachelor's degree in Electrical Engineering.
UVM, C, SystemC, DPI-C, SystemVerilog, Matlab
18h
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Sr. Staff Engineer - Digital Design Verification
Austin or Hsinchu or Shanghai or Shenzhen or Singapore
OnsiteFull Time
8+ YOEBSEE or MSEE and 8–12 years of digital design verification experience; multiple successful tape-outs; expertise in SoC verification, UVM/SystemVerilog, C/C++, automation, coverage, and complex IP integration.
SystemVerilog, Universal Verification Methodology (UVM), Verilog, C, C++, Python, Perl, Makefile, ARM, RISC-V, AMBA, AXI, AHB, APB, DMA
4w
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Silicon Design Verification Manager
Austin, Texas, United States
$192k-$278k/yr HybridFull Time
8+ YOE8+ years verification experience, degree in EE/CS/CE, expertise in advanced verification methodologies, processor architecture, System Verilog or C++, testbench design, and simulation-based verification.
System Verilog, C++
2mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
3mo
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Member of Technical Staff, Hardware, Design Verification Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOE5+ years industry experience, BS in EE/CE/CS, deep SystemVerilog and UVM experience, verification methodology expertise, familiarity with emulation/prototyping and formal methods, strong collaboration and debugging skills.
SystemVerilog, UVM, ZeBu, HAPS, Palladium, Protium, Python, Perl, Bash, TCL, SVA, Jasper, VC Formal, AXI, CHI
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