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181 layout engineer jobs at 74 companies in Gilroy, CA

2mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
Neurophos
Neurophos: Develops high-performance photonic processors for AI inference acceleration.
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
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1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
8+ YOE8+ years PCB layout experience, expert in Cadence Allegro, high-speed design, SI/PI and impedance control, HDI and manufacturing knowledge, ability to lead layout planning and mentor junior designers.
Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
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1mo
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Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Washington or Arizona or Oregon or California
$136k-$259k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEB.S. in Electrical Engineering (or equivalent), 5+ years PCB/layout experience (graphics cards, motherboards, HDI preferred), substrate layout experience, Cadence APD/SiP and Constraint Manager experience, high-speed signal integrity knowledge; Virtuoso/Calibre/Valor a plus.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor
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1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
8+ YOE8+ years PCB layout experience; expert in Cadence Allegro and Constraint Manager; strong high-speed design, SI/PI, HDI, impedance control, and PCB manufacturing knowledge.
Cadence Design Systems, Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
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1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
8+ YOE8+ years PCB layout experience with expert Cadence Allegro proficiency, high-speed design, impedance/stackup planning, HDI, EMI/EMC, PCB fabrication knowledge, and mentoring experience.
Cadence Design Systems, Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
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11h
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Package Design & Layout Engineer
Palo Alto, California, United States
OnsiteFull Time
Cspeed IO
Cspeed IO: A stealth startup developing next-generation optical semiconductor solutions for AI infrastructure.
6+ YOE6+ years IC package physical design experience, BS/MS in electrical engineering, expertise in package layout tools, multi-die packaging, substrate stack-ups, DFM/DF A closure, and English fluency.
Cadence Allegro Package Designer, APD+, Siemens Xpedition Package Designer, Synopsys IC Package, SKILL, Python, Cadence Sigrity, PowerSI, Ansys, Virtuoso, KLayout, AutoCAD, Cadence Integrity 3D-IC
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3w
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Layout Design Engineer (SRAM)
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
Wipro
WiproNYSE: WIT: Global technology services and consulting for digital transformation.
10+ YOEBSEE or equivalent, 10+ years custom IC layout experience with 5+ years in SRAM/memory IP, advanced-node (FinFET/GAA) experience, Cadence Virtuoso and Calibre/ICV proficiency, DRC/LVS debugging, mentoring ability.
Cadence Virtuoso, Calibre, ICV
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6d
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Staff Engineer, PCB Layout
San Jose, California, United States
$150k-$240k/yr OnsiteFull Time
Celestica
CelesticaNYSE: CLS: Provides design, manufacturing, and supply chain solutions for electronics.
7+ YOE7+ years PCB layout experience with Cadence Allegro (16.x/17.x), high-density and high-speed designs, knowledge of PCB/PCBA manufacturing, IPC standards, signal integrity, EMC/EMI; bachelor's degree or equivalent.
Cadence Allegro, Valor Trilogy 5000
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1w
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Senior / Principal Layout Engineer – Module Architecture (Pathfinding)
San Jose, California, United States
$202k-$344k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
8+ YOEBachelor's in Electrical Engineering,8+ years high-speed PCB layout experience, expertise in DDR/LPDDR, SI/PI and PDN, proficiency with Cadence Allegro/OrCAD and AI tools, ability to influence architecture decisions.
Cadence Allegro, OrCAD, AI tools
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2mo
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Senior Photonic Layout Design Engineer
Santa Clara, California, United States
$132k-$236k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
6+ YOEBS/MS/PhD in Electrical Engineering or Physics; 6+ years full-chip layout experience; Cadence Virtuoso; silicon photonics; layout automation scripting; DRC/LVS proficiency.
Cadence Virtuoso, Calibre, ICV, Dracula, PrimeYield, Python, SKILL, Perl, TCL, C++
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1mo
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Layout Verification / PEX Engineer
Palo Alto, California, United States
$150k-$170k/yr OnsiteFull Time
PsiQuantum
PsiQuantum: Builds fault-tolerant quantum computers using silicon photonics technology.
Bachelor's in EE/Physics/Microelectronics or equivalent; basic IC layout and verification knowledge; exposure to DRC/LVS/pex; familiarity with Linux/Unix; attention to detail and communication skills; interest in quantum computing.
Cadence Virtuoso, Siemens Calibre, Cadence Pegasus/PVS, Cadence Quantus, Python, Linux, Unix, EDA tools
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1w
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Senior / Principal Layout Engineer – Module Architecture (Pathfinding)
San Jose, California, United States
$202k-$344k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
8+ YOE8+ years high-speed PCB/layout experience, expertise in DDR/LPDDR interfaces, SI/PI and PDN, proficiency with Cadence Allegro/OrCAD, and experience influencing architecture decisions in pathfinding environments.
Cadence Allegro, OrCAD, AI tools
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1mo
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Staff PCB Layout Design Engineer
Mountain View or Sunnyvale
$218k-$245k/yr HybridFull Time
General Motors
General MotorsNYSE: GM: Manufactures and sells automobiles and automotive parts globally.
10+ YOEBachelor's in engineering required; 10 years experience in PCB layout and related roles; 8 years with design tools including Mentor Graphics; experience with HDI, high-power boards, high-speed buses, DFM/DFT, and leading design/supplier teams.
Mentor Graphics, ECAD
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2mo
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Staff Custom Analog Layout Engineer
San Jose or United States
$139k-$259k/yr HybridFull Time
Nokia
NokiaNYSE: NOK: Sells telecommunications infrastructure and software for global network operators.
10+ YOEBS degree or equivalent; 10+ years in analog/mixed-signal layout design; proficient with layout tools and DRC/LVS/ERC flows.
Virtuoso, Laker, Calibre, PVS, IC Validator, DRC/LVS/ERC tools, RC extraction, EM/IR analysis
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1w
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Layout (FIRE) Extraction Engineer
Milpitas, California, United States
$120k-$160k/yr OnsiteFull Time
PDF Solutions
PDF SolutionsNASDAQ: PDFS: Data analytics platform for semiconductor yield improvement.
Bachelor's in electrical engineering or related, experience with OPC/RET and mask/CMOS processes, scripting (Python/Perl/Tcl/Shell), Linux, and collaboration with design/lithography/fab teams.
Mentor Graphics Calibre OPC/ILT, Synopsys Sentaurus/Litho, ASML Brion Tachyon, Cadence, Synopsys, KLayout, Linux, Python, Perl, Tcl, Shell
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1mo
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Sr PCB Layout Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or New York or San Diego
$137k-$214k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
7+ YOEBachelor's degree or equivalent, 7+ years PCB layout experience, 5+ years high-speed circuit experience, experience managing multiple projects, U.S. work-authorization required; Mentor Xpedition experience preferred.
Mentor Xpedition
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2mo
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Analog/RF IC Layout Design Engineer
Colorado Springs or Santa Clara
$120k-$200k/yr OnsiteFull Time
Keysight Technologies
Keysight TechnologiesNYSE: KEYS: Provides electronic design, test, and simulation software and hardware.
7+ YOEBS/MS in Electrical Engineering; 7+ years analog IC layout; 5+ years Cadence Virtuoso Layout XL; DRC/LVS/meter densities; BiCMOS 130 nm+; device matching knowledge; multi-design capability; SVN/Cliosoft/SOS experience; strong teamwork.
Cadence Virtuoso, DRC, LVS, Mentor Calibre, OCEAN, Scripting
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1mo
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
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2w
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RFIC Layout Designer (RFIC Engineering)
Redmond or Irvine or Palo Alto
OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
1+ YOEIC layout experience for RF/analog designs, 1+ years professional layout or 3+ years without degree; skills in analog/RF layout, advanced-node processes, scripting, revision control, and Linux; ITAR eligibility required.
Skill, shell scripting, Perl, Python, Linux, GDS
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1d
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Senior Custom Memory Layout Design Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOEDegree in EE/CE/CS (or equivalent) with 1+ to 5+ years experience depending on degree; experience in custom SRAM/RF/cache layout, physical verification, signoff, scripting (Python, SKILL, TCL, Perl) and advanced-node processes; must pass Microsoft cloud background and export-control eligibility checks.
Cadence Virtuoso, Siemens/Mentor Calibre, Ansys Totem, Cadence Voltus, Python, SKILL, TCL, Perl
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