HiringCafe
Join our community

112 layout engineer jobs at 44 companies in Salinas, CA

2mo
Save
Mark Applied
Hide
Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
Neurophos
Neurophos: Develops high-performance photonic processors for AI inference acceleration.
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
Job PostingView all
1mo
Save
Mark Applied
Hide
Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Washington or Arizona or Oregon or California
$136k-$259k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEB.S. in Electrical Engineering (or equivalent), 5+ years PCB/layout experience (graphics cards, motherboards, HDI preferred), substrate layout experience, Cadence APD/SiP and Constraint Manager experience, high-speed signal integrity knowledge; Virtuoso/Calibre/Valor a plus.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor
Job PostingView all
3w
Save
Mark Applied
Hide
Layout Design Engineer (SRAM)
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
Wipro
WiproNYSE: WIT: Global technology services and consulting for digital transformation.
10+ YOEBSEE or equivalent, 10+ years custom IC layout experience with 5+ years in SRAM/memory IP, advanced-node (FinFET/GAA) experience, Cadence Virtuoso and Calibre/ICV proficiency, DRC/LVS debugging, mentoring ability.
Cadence Virtuoso, Calibre, ICV
Job PostingView all
6d
Save
Mark Applied
Hide
Staff Engineer, PCB Layout
San Jose, California, United States
$150k-$240k/yr OnsiteFull Time
Celestica
CelesticaNYSE: CLS: Provides design, manufacturing, and supply chain solutions for electronics.
7+ YOE7+ years PCB layout experience with Cadence Allegro (16.x/17.x), high-density and high-speed designs, knowledge of PCB/PCBA manufacturing, IPC standards, signal integrity, EMC/EMI; bachelor's degree or equivalent.
Cadence Allegro, Valor Trilogy 5000
Job PostingView all
1w
Save
Mark Applied
Hide
Senior / Principal Layout Engineer – Module Architecture (Pathfinding)
San Jose, California, United States
$202k-$344k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
8+ YOEBachelor's in Electrical Engineering,8+ years high-speed PCB layout experience, expertise in DDR/LPDDR, SI/PI and PDN, proficiency with Cadence Allegro/OrCAD and AI tools, ability to influence architecture decisions.
Cadence Allegro, OrCAD, AI tools
Job PostingView all
2mo
Save
Mark Applied
Hide
Senior Photonic Layout Design Engineer
Santa Clara, California, United States
$132k-$236k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
6+ YOEBS/MS/PhD in Electrical Engineering or Physics; 6+ years full-chip layout experience; Cadence Virtuoso; silicon photonics; layout automation scripting; DRC/LVS proficiency.
Cadence Virtuoso, Calibre, ICV, Dracula, PrimeYield, Python, SKILL, Perl, TCL, C++
Job PostingView all
1w
Save
Mark Applied
Hide
Senior / Principal Layout Engineer – Module Architecture (Pathfinding)
San Jose, California, United States
$202k-$344k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
8+ YOE8+ years high-speed PCB/layout experience, expertise in DDR/LPDDR interfaces, SI/PI and PDN, proficiency with Cadence Allegro/OrCAD, and experience influencing architecture decisions in pathfinding environments.
Cadence Allegro, OrCAD, AI tools
Job PostingView all
2mo
Save
Mark Applied
Hide
Staff Custom Analog Layout Engineer
San Jose or United States
$139k-$259k/yr HybridFull Time
Nokia
NokiaNYSE: NOK: Sells telecommunications infrastructure and software for global network operators.
10+ YOEBS degree or equivalent; 10+ years in analog/mixed-signal layout design; proficient with layout tools and DRC/LVS/ERC flows.
Virtuoso, Laker, Calibre, PVS, IC Validator, DRC/LVS/ERC tools, RC extraction, EM/IR analysis
Job PostingView all
2mo
Save
Mark Applied
Hide
Analog/RF IC Layout Design Engineer
Colorado Springs or Santa Clara
$120k-$200k/yr OnsiteFull Time
Keysight Technologies
Keysight TechnologiesNYSE: KEYS: Provides electronic design, test, and simulation software and hardware.
7+ YOEBS/MS in Electrical Engineering; 7+ years analog IC layout; 5+ years Cadence Virtuoso Layout XL; DRC/LVS/meter densities; BiCMOS 130 nm+; device matching knowledge; multi-design capability; SVN/Cliosoft/SOS experience; strong teamwork.
Cadence Virtuoso, DRC, LVS, Mentor Calibre, OCEAN, Scripting
Job PostingView all
1mo
Save
Mark Applied
Hide
Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
Job PostingView all
1mo
Save
Mark Applied
Hide
Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel
Job PostingView all
1mo
Save
Mark Applied
Hide
Principal/Senior High-Speed Analog Layout Engineer
Irvine or San Jose or Ottawa
OnsiteFull Time
Celero Communications
Celero Communications: Developing high-performance coherent DSP technology for AI connectivity.
10+ YOE10+ years analog/mixed-signal layout experience in advanced CMOS/FinFET (TSMC preferred), expertise with Cadence Virtuoso, Calibre, Pegasus, LVS/DRC/PERC/ERC flows, and leadership/mentoring experience; scripting with SKILL/TCL/Python a plus.
Cadence Virtuoso, Calibre, Pegasus, SKILL, TCL, Python
Job PostingView all
2mo
Save
Mark Applied
Hide
Analog/RF IC Layout Design Engineer.
Colorado Springs or Santa Clara
$118k-$196k/yr OnsiteFull Time
Keysight Technologies
Keysight TechnologiesNew York Stock Exchange: KEYS: Manufactures hardware and software for electronic test and measurement.
7+ YOEBS/MS in Electrical Engineering or equivalent,7+ years custom analog IC layout experience,5+ years Cadence Virtuoso Layout XL,sub-micron BiCMOS knowledge,device matching,version control experience,US export-control restrictions apply.
Cadence Virtuoso Layout XL, SVN, Cliosoft/SOS, Mentor Calibre, Linux, SKILL, OCEAN
Job PostingView all
1w
Save
Mark Applied
Hide
IC Package Layout Team Leader
San Jose, California, United States
$211k-$305k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
5+ YOEDegree in electrical engineering with relevant experience, 5+ years package/layout experience, high-speed routing and PDN knowledge, EDA tool proficiency, and leadership/mentorship experience.
Cadence APD+, Python, Perl, TCL
Job PostingView all
1w
Save
Mark Applied
Hide
Sr. Staff Engineer, Analog/Mixed-Signal Design
San Jose, California, United States
$180k-$223k/yr OnsiteFull Time
Ayar Labs
Ayar Labs: Develops optical interconnect technology for high-speed data movement.
6+ YOEM.S. in Electrical Engineering,6+ years analog/mixed-signal design,experience with high-speed analog blocks and FinFET CMOS,proficient with Cadence/ADE/Layout/Spectre;Python and SKILL preferred.
Cadence, ADE, Layout, Spectre, Python, SKILL
Job PostingView all
1w
Save
Mark Applied
Hide
Industrial Engineer
Santa Clara, California, United States
$120k-$145k/yr OnsiteFull Time
eCMMS
eCMMS: Provides electronics packaging and reverse logistics for major manufacturers.
4+ YOEBachelor's in industrial engineering, 4+ years factory layout/manufacturing engineering experience, AutoCAD proficiency, simulation/digital twin familiarity, strong analytical and communication skills.
AutoCAD, FlexSim, AnyLogic, Plant Simulation, NVIDIA Omniverse
Job PostingView all
1d
Save
Mark Applied
Hide
Packaging Design Engineer
San Jose or San Diego
HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experienced package engineer with CAD/simulation tool proficiency, package/PCB layout and power integrity expertise, scripting ability, and engineering degree.
Cadence, SKILL, Ansys, AutoCAD
Job PostingView all
1w
Save
Mark Applied
Hide
Hardware Design Engineer
San Jose, California, United States
$91k-$105k/yr OnsiteFull Time
Supermicro
SupermicroNASDAQ: SMCI: Designs and manufactures high-performance server and storage solutions.
Design and test server motherboards and add-on cards; schematics capture, PCB layout, BOM creation, debugging, and documentation. Bachelor's in electrical engineering preferred; strong circuit and PCB knowledge required.
Job PostingView all
2mo
Save
Mark Applied
Hide
Physical Verification Engineer
Phoenix or Santa Clara or Hillsboro
$129k-$245k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
3+ YOEUS citizenship, ability to obtain US government security clearance, Bachelor in Electrical/Computer Engineering or STEM, 3+ years in CMOS processes and layout verification, 3+ years in parasitic extraction and scripting
Python, Perl, Tcl, Shell, StarRC, Quantus, xACT, ICV, Calibre, Pegasus, LVS, DRC, ERC, PERC, Parasitic Extraction Tools
Job PostingView all
1mo
Save
Mark Applied
Hide
Hardware Engineer, Power Management / Battery / BMS
San Jose, California, United States
$160k-$190k/yr OnsiteFull Time
Rivet Industries
Rivet Industries: Building integrated task systems for frontline industrial and defense operators.
0+ YOEDegree in Electrical or Computer Engineering, 0–3 years hardware design experience (power management/battery/BMS preferred), Cadence experience for schematic/PCB layout, US Person required.
Cadence
Job PostingView all

Explore Jobs

Expand Your Job Search