198 layout jobs at 84 companies in Gilroy, CA
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Layout Designer
San Jose, California, United States
$46-$106/hr OnsiteFull Time
5+ YOEAS in Electronics/Electrical Engineering plus 5+ years semiconductor layout experience; deep knowledge of EDA tools (Cadence Virtuoso, Synopsys, Calibre); strong debugging, physical verification, layout and floor/planning skills; strong communication.
EDA tools, Cadence Virtuoso, Synopsys, Calibre, Agentic AI
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Senior Layout Designer
San Jose, California, United States
$63-$120/hr OnsiteFull Time
10+ YOEAssociate degree in electronics/electrical engineering plus 10 years layout experience; deep EDA tool knowledge; strong debugging, verification, communication, and layout methodology skills.
Cadence Virtuoso, Synopsys, Calibre
2w
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RFIC Layout Designer (RFIC Engineering)
Redmond or Irvine or Palo Alto
OnsiteFull Time
1+ YOEIC layout experience for RF/analog designs, 1+ years professional layout or 3+ years without degree; skills in analog/RF layout, advanced-node processes, scripting, revision control, and Linux; ITAR eligibility required.
Skill, shell scripting, Perl, Python, Linux, GDS
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience, expert in Cadence Allegro, high-speed design, SI/PI and impedance control, HDI and manufacturing knowledge, ability to lead layout planning and mentor junior designers.
Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
16h
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PCB Layout Engineer
Mountain View, California, United States
$200k-$275k/yr OnsiteFull Time
8+ YOERequires 8+ years of complex high-speed, high-current PCB layout experience, constraint-driven design expertise, and hands-on experience with Cadence Allegro, Siemens Xpedition, Altium, or equivalent tools.
Cadence Allegro, Siemens Xpedition, Altium, Gerber, ODB++, IPC-2581, CoWoS, EMIB, HBM, IPC CID, IPC CID+
1d
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Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Washington or Arizona or Oregon or California
$136k-$259k/yr HybridFull Time
5+ YOEBachelor's degree in electrical engineering or equivalent experience, 5+ years of PCB layout experience, and expertise with Cadence APD or SiP, high-speed design, substrate layout, and PCB layout tools.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor, CAD
2mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
1d
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Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Oregon or Arizona or Washington or California
$136k-$259k/yr HybridFull Time
5+ YOEBachelor's degree in electrical engineering or equivalent experience; 5+ years in PCB layout; substrate layout, Cadence APD or SiP, high-speed signal integrity, and related CAD tools required or preferred.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience; expert in Cadence Allegro and Constraint Manager; strong high-speed design, SI/PI, HDI, impedance control, and PCB manufacturing knowledge.
Cadence Design Systems, Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience with expert Cadence Allegro proficiency, high-speed design, impedance/stackup planning, HDI, EMI/EMC, PCB fabrication knowledge, and mentoring experience.
Cadence Design Systems, Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
3w
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Layout Design Engineer (SRAM)
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
10+ YOEBSEE or equivalent, 10+ years custom IC layout experience with 5+ years in SRAM/memory IP, advanced-node (FinFET/GAA) experience, Cadence Virtuoso and Calibre/ICV proficiency, DRC/LVS debugging, mentoring ability.
Cadence Virtuoso, Calibre, ICV
1w
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Staff Engineer, PCB Layout
San Jose, California, United States
$150k-$240k/yr OnsiteFull Time
7+ YOE7+ years PCB layout experience with Cadence Allegro (16.x/17.x), high-density and high-speed designs, knowledge of PCB/PCBA manufacturing, IPC standards, signal integrity, EMC/EMI; bachelor's degree or equivalent.
Cadence Allegro, Valor Trilogy 5000
2mo
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Staff Custom Analog Layout Engineer
San Jose or United States
$139k-$259k/yr HybridFull Time
10+ YOEBS degree or equivalent; 10+ years in analog/mixed-signal layout design; proficient with layout tools and DRC/LVS/ERC flows.
Virtuoso, Laker, Calibre, PVS, IC Validator, DRC/LVS/ERC tools, RC extraction, EM/IR analysis
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Layout Verification / PEX Engineer
Palo Alto, California, United States
$150k-$170k/yr OnsiteFull Time
Bachelor's in EE/Physics/Microelectronics or equivalent; basic IC layout and verification knowledge; exposure to DRC/LVS/pex; familiarity with Linux/Unix; attention to detail and communication skills; interest in quantum computing.
Cadence Virtuoso, Siemens Calibre, Cadence Pegasus/PVS, Cadence Quantus, Python, Linux, Unix, EDA tools
2d
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Package Design & Layout Engineer
Palo Alto, California, United States
OnsiteFull Time
6+ YOE6+ years IC package physical design experience, BS/MS in electrical engineering, expertise in package layout tools, multi-die packaging, substrate stack-ups, DFM/DF A closure, and English fluency.
Cadence Allegro Package Designer, APD+, Siemens Xpedition Package Designer, Synopsys IC Package, SKILL, Python, Cadence Sigrity, PowerSI, Ansys, Virtuoso, KLayout, AutoCAD, Cadence Integrity 3D-IC
2w
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IC Package Layout Team Leader
San Jose, California, United States
$211k-$305k/yr HybridFull Time
5+ YOEDegree in electrical engineering with relevant experience, 5+ years package/layout experience, high-speed routing and PDN knowledge, EDA tool proficiency, and leadership/mentorship experience.
Cadence APD+, Python, Perl, TCL
1mo
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Sr PCB Layout Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or New York or San Diego
$137k-$214k/yr OnsiteFull Time
7+ YOEBachelor's degree or equivalent, 7+ years PCB layout experience, 5+ years high-speed circuit experience, experience managing multiple projects, U.S. work-authorization required; Mentor Xpedition experience preferred.
Mentor Xpedition
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Staff PCB Layout Design Engineer
Mountain View or Sunnyvale
$218k-$245k/yr HybridFull Time
10+ YOEBachelor's in engineering required; 10 years experience in PCB layout and related roles; 8 years with design tools including Mentor Graphics; experience with HDI, high-power boards, high-speed buses, DFM/DFT, and leading design/supplier teams.
Mentor Graphics, ECAD
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IC Layout Automation Software Engineer
Fremont, California, United States
$190k-$220k/yr OnsiteFull Time
BS (or higher) in a technical field, strong Python proficiency, experience with IC layout formats (GDSII) and EDA tools (KLayout, gdspy, Cadence), familiarity with semiconductor fabrication and lithography, and experience owning production software.
Python, GDSII, KLayout, gdspy, Cadence, EDA
2mo
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Analog/RF IC Layout Design Engineer.
Colorado Springs or Santa Clara
$118k-$196k/yr OnsiteFull Time
7+ YOEBS/MS in Electrical Engineering or equivalent,7+ years custom analog IC layout experience,5+ years Cadence Virtuoso Layout XL,sub-micron BiCMOS knowledge,device matching,version control experience,US export-control restrictions apply.
Cadence Virtuoso Layout XL, SVN, Cliosoft/SOS, Mentor Calibre, Linux, SKILL, OCEAN
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