123 layout jobs at 49 companies in Salinas, CA
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Layout Designer
San Jose, California, United States
$46-$106/hr OnsiteFull Time
5+ YOEAS in Electronics/Electrical Engineering plus 5+ years semiconductor layout experience; deep knowledge of EDA tools (Cadence Virtuoso, Synopsys, Calibre); strong debugging, physical verification, layout and floor/planning skills; strong communication.
EDA tools, Cadence Virtuoso, Synopsys, Calibre, Agentic AI
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Senior Layout Designer
San Jose, California, United States
$63-$120/hr OnsiteFull Time
10+ YOEAssociate degree in electronics/electrical engineering plus 10 years layout experience; deep EDA tool knowledge; strong debugging, verification, communication, and layout methodology skills.
Cadence Virtuoso, Synopsys, Calibre
1d
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Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Washington or Arizona or Oregon or California
$136k-$259k/yr HybridFull Time
5+ YOEBachelor's degree in electrical engineering or equivalent experience, 5+ years of PCB layout experience, and expertise with Cadence APD or SiP, high-speed design, substrate layout, and PCB layout tools.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor, CAD
2mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
3w
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Layout Design Engineer (SRAM)
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
10+ YOEBSEE or equivalent, 10+ years custom IC layout experience with 5+ years in SRAM/memory IP, advanced-node (FinFET/GAA) experience, Cadence Virtuoso and Calibre/ICV proficiency, DRC/LVS debugging, mentoring ability.
Cadence Virtuoso, Calibre, ICV
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Staff Engineer, PCB Layout
San Jose, California, United States
$150k-$240k/yr OnsiteFull Time
7+ YOE7+ years PCB layout experience with Cadence Allegro (16.x/17.x), high-density and high-speed designs, knowledge of PCB/PCBA manufacturing, IPC standards, signal integrity, EMC/EMI; bachelor's degree or equivalent.
Cadence Allegro, Valor Trilogy 5000
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Staff Custom Analog Layout Engineer
San Jose or United States
$139k-$259k/yr HybridFull Time
10+ YOEBS degree or equivalent; 10+ years in analog/mixed-signal layout design; proficient with layout tools and DRC/LVS/ERC flows.
Virtuoso, Laker, Calibre, PVS, IC Validator, DRC/LVS/ERC tools, RC extraction, EM/IR analysis
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PCB Design Layout Engineer
Santa Clara, California, United States
$168k-$322k/yr OnsiteFull Time
6+ YOEB.Sc. in EE (or equivalent experience), 6+ years relevant experience, leadership experience, PCB layout of high-speed/high-density boards, knowledge of SI/EMI and regulatory standards, strong communication and problem-solving.
Cadence Allegro, Mentor Graphics, ODB++
2w
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IC Package Layout Team Leader
San Jose, California, United States
$211k-$305k/yr HybridFull Time
5+ YOEDegree in electrical engineering with relevant experience, 5+ years package/layout experience, high-speed routing and PDN knowledge, EDA tool proficiency, and leadership/mentorship experience.
Cadence APD+, Python, Perl, TCL
2mo
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Analog/RF IC Layout Design Engineer.
Colorado Springs or Santa Clara
$118k-$196k/yr OnsiteFull Time
7+ YOEBS/MS in Electrical Engineering or equivalent,7+ years custom analog IC layout experience,5+ years Cadence Virtuoso Layout XL,sub-micron BiCMOS knowledge,device matching,version control experience,US export-control restrictions apply.
Cadence Virtuoso Layout XL, SVN, Cliosoft/SOS, Mentor Calibre, Linux, SKILL, OCEAN
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Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel
1w
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Design custom digital macros and libraries for state-of-the-art ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
CAD, ASIC
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Principal/Senior High-Speed Analog Layout Engineer
Irvine or San Jose or Ottawa
OnsiteFull Time
10+ YOE10+ years analog/mixed-signal layout experience in advanced CMOS/FinFET (TSMC preferred), expertise with Cadence Virtuoso, Calibre, Pegasus, LVS/DRC/PERC/ERC flows, and leadership/mentoring experience; scripting with SKILL/TCL/Python a plus.
Cadence Virtuoso, Calibre, Pegasus, SKILL, TCL, Python
3w
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Head of Cinematography, Layout- Ink
Los Angeles or Vancouver or Los Gatos
$75/hr OnsiteFull Time
7+ YOE4+ Mgmt7+ years in film/TV/games, 4+ years leading teams, credits in layout/previs, knowledge of previs/camera/CG shot production, Maya/Houdini/Nuke, Python/MEL familiarity, GenAI tool interest, budget and timeline experience.
Autodesk Maya, Houdini, Nuke, Python, MEL
1w
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Sr. Staff Engineer, Analog/Mixed-Signal Design
San Jose, California, United States
$180k-$223k/yr OnsiteFull Time
6+ YOEM.S. in Electrical Engineering,6+ years analog/mixed-signal design,experience with high-speed analog blocks and FinFET CMOS,proficient with Cadence/ADE/Layout/Spectre;Python and SKILL preferred.
Cadence, ADE, Layout, Spectre, Python, SKILL
2mo
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Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
Hillsboro or Santa Clara or Austin
$142k-$200k/yr HybridFull Time
5+ YOEMaster's degree in electrical engineering or related field; 5+ years in physical/layout design, advanced nodes; proficiency with layout tools; floorplanning and design verification.
Cadence Virtuoso Suite, Synopsys Custom Compiler
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RFIC Design Intern
San Jose, California, United States
OnsiteMultiple Commitments Available
2+ YOECurrently pursuing M.S. or Ph.D. in Electrical Engineering, 2+ years RFIC design experience, familiarity with CMOS/SOI/SiGe, RF layout and post-layout simulation, Cadence Virtuoso, Spectre RF, ADS, Python or MATLAB.
Cadence Virtuoso, Spectre RF, ADS, Python, MATLAB
3mo
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Sales FAE
San Jose, California, United States
HybridFull Time
BS in electrical engineering; MS preferred; experience with electronic components; board design/layout; good English; travel willingness.
MS Office, Oscilloscope, DVM, Signal Generator
2mo
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Art Director
Hong Kong or San Jose
OnsiteFull Time
5+ YOE5+ years in design/art direction; strong typography, layout, color; leadership with hands-on execution; game or creative design experience a plus.
2mo
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Senior Principal Electrical Engineer
Santa Clara, California, United States
$128k-$224k/yr HybridFull Time
15+ YOE15+ years in RF/microwave, high-speed mixed-signal hardware design and PCB layout; strong leadership; optical/transceiver experience.
RF design, High-speed PCB design, SI/PI, EDA/CAD, Test equipment, Optical transceivers, MATLAB, Python
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