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60 packaging design engineer jobs at 25 companies in Salinas, CA

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Packaging Design Engineer
San Jose or San Diego
HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experienced package engineer with CAD/simulation tool proficiency, package/PCB layout and power integrity expertise, scripting ability, and engineering degree.
Cadence, SKILL, Ansys, AutoCAD
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3mo
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Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
TransPak: Packaging solutions provider
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
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1mo
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Advanced Packaging Design Engineer
Santa Clara or Chandler
$192k-$287k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
5+ YOEBS/MS/PhD in engineering,5-10 years advanced packaging design experience, expertise with Cadence APD, high-speed interfaces, substrate and assembly processes, and cross-functional collaboration.
Cadence APD, AutoCAD
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2mo
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Applied Materials
Applied MaterialsNASDAQ: AMAT: Manufacturers of equipment for semiconductor and display production.
Experience in packaging engineering including supplier management, test plan development and lab testing, Design for Transportability (DFT), packaging standards, continuous improvement, and ability to lead projects.
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2mo
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Applied Materials
Applied MaterialsNASDAQ: AMAT: Produces equipment and services for chip and display manufacturing.
Packaging engineering experience with supplier management, test plan development, Design For Transportability (DFT), standards development, continuous improvement, and ability to train others; travel ~10%.
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2mo
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Manufacturing Design Engineer (MDE) - Packaging
Cupertino, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designing and manufacturing consumer electronics, software, and digital services.
Managing R&D, selection, and implementation of manufacturing processes for consumer packaging parts and assemblies; strong product and process engineering skills.
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Packaging Tech Lead Design Engineer
San Jose, California, United States
$185k-$240k/yr OnsiteFull Time
Astera Labs
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
5+ YOEBachelor's degree in electrical or computer engineering and 5+ years of digital design experience, including a full chip from specification to tapeout. Requires Verilog/SystemVerilog, RTL, synthesis, timing closure, CDC, lint, and low-power expertise.
Verilog, SystemVerilog, RTL, CDC, DFT, BIST, PCIe, CXL, Ethernet, NVLink, UALink, UCIe, COSMOS, SoC
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Principal Packaging Engineer, Optical Interfaces
Santa Clara, California, United States
$145k-$255k/yr OnsiteFull Time
nEye Systems
nEye Systems: Develops MEMS-based silicon photonics optical circuit switches for data centers.
10+ YOE10+ years packaging design experience for optical/photonic components, experience with PIC edge coupling, reliability engineering, CAD and FEA usage, and working with contract manufacturers.
CAD, FEA
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2mo
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Staff Semi Packaging Engineer
San Jose, California, United States
$130k-$188k/yr OnsiteFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
CAD
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Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Multinational technology focused on e-commerce and cloud computing.
5+ YOEBachelor's degree in electrical engineering or related field and 5+ years of IC package layout and physical design experience. Requires package layout tools, advanced packaging, DFM, and physical verification expertise.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, Perl, ARM, TCL, Skill, Ravel, DRC
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Package Design Methodology Engineer
Santa Clara or Austin or California
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBS or equivalent and 5+ years developing package design flows; strong Python/C++ skills; experience applying AI/ML and LLMs in engineering workflows; solid VLSI package design fundamentals.
Python, C++, LLMs, EDA, AI/ML
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Package Design Engineer
San Jose or Austin or Fort Collins
$122k-$195k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
6+ YOEBSEE with 8+ years or MSEE with 6+ years in flip-chip BGA package design; knowledge of package signal and power integrity; Cadence APD and Cadence SKILL experience preferred; project management and collaboration skills.
Cadence APD, Cadence SKILL
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Package Design Methodology Engineer
Santa Clara or Austin or United States
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOEBS in CS/EE or equivalent,5+ years developing package design flows/methodologies,proficiency in Python and/or C++,knowledge of VLSI package electrical fundamentals,experience applying AI/ML or LLMs in engineering workflows.
Python, C++, LLMs, EDA
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IC Package Design Engineer
San Jose, California, United States
$153k-$219k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
3+ YOEBachelor's (5+ years) or Master’s (3+ years) in Electrical Engineering or related field; experience in package/PCB/high-speed design, power delivery, and EDA tools; scripting (Python, Perl, TCL, shell) and strong collaboration skills.
EDA, Python, Perl, TCL, Shell
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3mo
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Advanced Packaging SI/PI Engineer
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Etched
Etched: Private semiconductor startup building AI inference chips, racks, and software for frontier-model customers.
8+ YOEBachelor's or Master's in Electrical/Computer Engineering; 8+ years SI/PI experience on high-performance ASIC/accelerator platforms; PDN design, high-speed interfaces; proficiency with SI/PI tools; packaging/OSAT/ODM collaboration.
ANSYS HFSS, SIwave, Cadence Sigrity, Keysight ADS
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1mo
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Package Design Engineer - Staff
Santa Clara or San Diego
$154k-$253k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
5+ YOEExperience in IC package/SIP physical design, Cadence APD/Allegro proficiency, familiarity with SI/PI tools (HFSS, PowerSI, Q3D), package verification and CAD tool development; master\u0002s preferred with 5+ years.
Cadence APD, Cadence Allegro, PCB Editor, Advanced Package Designer, APD/SiP, XtractIM, PowerSI, HFSS, Q3D, Calibre
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1mo
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Principal Package Design Engineer
San Jose, California, United States
$195k-$240k/yr HybridFull Time
Renesas Electronics
Renesas ElectronicsTokyo Stock Exchange: 6723: Designs and manufactures semiconductors for automotive and industrial systems.
5+ YOEMSc/PhD in engineering, 5+ years semiconductor packaging experience, expertise in advanced packaging architectures, reliability testing, thermal/mechanical/electrical analysis, OSAT collaboration, and project leadership.
Cadence Allegro Package Designer, Solid works, ANSYS, COMSOL, JMP, Minitab
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2mo
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Sr. Engineer, Package Design
Santa Clara, California, United States
$139k-$191k/yr OnsiteFull Time
SiTime
SiTimeNASDAQ: SITM: Precision timing developing MEMS-based silicon timing solutions.
5+ YOEM.S. or PhD in Mechanical Engineering/Materials Science or related field; 5+ years semiconductor IC packaging experience; experience with OSATs, flip-chip/leadframe/substrate packages, thermal/stress/electrical modeling; AutoCAD experience.
AutoCAD
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2mo
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Mechanical Design Engineer
Morgan Hill or Melbourne or Lowell or North America or Europe or Asia
$82k-$131k/yr OnsiteFull Time
MACOM
MACOMNASDAQ: MTSI: Designs and manufactures semiconductor products for communications infrastructure.
5+ YOEMechanical engineering degree with 5+ years in electronics packaging/assembly, proficiency in SolidWorks/AutoCAD and thermal analysis (Icepak preferred), GD&T, machining, tolerance/material selection, vendor coordination, BOM and DFM experience.
SolidWorks, Icepak, AutoCAD, PCB layout viewers, GD&T
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2mo
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Sr. Engineer, Package Design
Santa Clara or Austin or Toronto or New Taipei City
$100k-$500k/yr HybridFull Time
Tenstorrent
Tenstorrent: Designs and manufactures AI processors and RISC-V CPU solutions.
3+ YOE3+ years experience with Cadence Allegro PCB Designer, PCB routing and BGA design, signal and power integrity knowledge, strong communication and cross-discipline collaboration skills.
Cadence Allegro PCB Designer
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