2mo
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Circuit Design Engineer
Annapolis Junction or Catonsville
$99k-$225k/yr OnsiteFull Time
10+ YOEExperience with Python, Verilog, C, C++, Bash, or Java; RTL/RTL design and timing analysis; FPGA experience; TS/SCI clearance with polygraph; Bachelor's in EE/SE/CE/CS with 10+ yrs or Master's with 5+ yrs designing ASICs.
Python, Verilog, C, C++, Bash, Java, RTL, FPGAs
2mo
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Programmable Logic Design Engineer
Germantown or Carlsbad or Independence or Englewood
$156k-$246k/yr OnsiteContract
5+ YOEBachelor's degree in Electrical/Computer Engineering; 5-8 years FPGA design; SystemVerilog; RTL design for signal processing; FPGA modules; strong communication; distribution teamwork.
System Verilog, Verilog, VHDL, Xilinx Vivado, RTL design, FPGA design, Testbench development, Simulation
2w
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Engineer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOE5+ years RTL FPGA design experience (VHDL/Verilog/SystemVerilog), experience implementing image/signal processing on FPGAs, Xilinx device experience, PCIe/CoaXPress/10GbE/DDR interfaces, MATLAB/Python/C++, Vitis HLS/AI, Linux driver experience, U.S. citizenship and ability to obtain clearance.
VHDL, Verilog, SystemVerilog, RTL, Xilinx Kintex, Xilinx Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, Vitis HLS, Vitis AI, MATLAB, Python, C++, Linux
2mo
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Circuit Design Engineer
Annapolis Junction or Catonsville
$99k-$225k/yr OnsiteFull Time
10+ YOETen+ years ASIC design experience; TS/SCI with poly; BS in EE/SE/CE/CS or MS with relevant experience; RTL, FPGA, Python/Verilog/C/C++, etc.
Python, Verilog, C, C++, Bash, Java, RTL, FPGAs
2mo
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FPGA Engineer (VA, Reston )
Reston, Virginia, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog; simulation, verification, system integration; verification tools and toolchains.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm
2mo
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FPGA Development Engineer, Bespoke Solutions
Jessup or Arlington or Herndon
$136k-$184k/yr OnsiteFull Time
5+ YOEBachelor's degree in Electrical Engineering; 5+ years design/architecture experience; RTL coding with VHDL/SystemVerilog/Verilog; knowledge of IT hardware and networks; 5+ years FPGA RTL development.
VHDL, SystemVerilog, Verilog, Xilinx Ultrascale+, Versal ACAP, Intel Agilex, FPGA design
1mo
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FPGA Developer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOEU.S. citizen able to obtain security clearance. 5+ years RTL FPGA design (VHDL/Verilog/SystemVerilog), FPGA implementation of image/signal processing, experience with Xilinx devices, high-speed interfaces, MATLAB/Python/C++, Vitis HLS/AI, and Linux driver development.
VHDL, Verilog, SystemVerilog, RTL, FPGA, Kintex, Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, MATLAB, Python, C++, Vitis HLS, Vitis AI, Linux
3w
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Digital Design Engineer - Level 5 - Linthicum
Linthicum, Maryland, United States
$186k-$279k/yr OnsiteFull Time
7+ YOEDegree in EE/CE/CS (Bachelor’s+12yr or Master’s+10yr or PhD+7yr), FPGA/ASIC/HDL (Verilog, VHDL) experience, FPGA IDEs (Xilinx, Microsemi), test/verification and RTL debug, mentoring skills, U.S. citizenship and ability to obtain Top Secret clearance.
Xilinx, Microsemi, HDL, Verilog, VHDL, RTL
3d
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Senior FPGA Developer
Severn, Maryland, United States
$123k-$245k/yr OnsiteFull Time
15+ YOEDesign and develop high-speed FPGA architectures, RTL/HDL coding, embedded firmware/RTOS, high-speed PCB integration, and mentor junior engineers; must obtain TS/SCI clearance.
Verilog, VHDL, Vivado, Lattice Diamond, Libero, Vitis HLS, Simulink, LabVIEW, Python, BERT
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
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Firmware Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in CE/EE/CS, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado/SoC FPGAs, TCP/UDP/IP and serial protocols, Bash/Python scripting; U.S. Person required.
Verilog, SystemVerilog, Vivado Design Suite, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, Bash, Python, git, Bitbucket CI, Jenkins
2w
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Senior FPGA Engineer
Fairfax, Virginia, United States
$76k-$141k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE (or MS) and 6+ years (4+ with MS) experience in FPGA RTL design, timing closure, simulation/verification, Vivado/VHDL/SystemVerilog experience, lab bring‑up, and high‑speed interface integration.
Xilinx, Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, Versal ACAP, Versal AI Engines, Vivado Design Suite, Vivado IP Integrator, Vivado HW Debugger, Chipscope, SmartDebug, Libero, Git, Modelsim, Questasim, Aldec, UVVM, UVM, OVM, VHDL, SystemVerilog, MATLAB, Simulink, Linux, C, C++
1mo
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Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
3w
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Electrical Engineer FPGA - Level 3/4 - Dulles
Dulles, Virginia, United States
$114k-$213k/yr OnsiteFull Time
5+ YOEExperience with VHDL and FPGA design flow, ability to obtain Top Secret/SCI clearance, degree in engineering with relevant years of experience, FPGA verification and architecture experience, and recent hands-on VHDL work.
VHDL, SystemVerilog, DSP, MATLAB, SimuLink, Xilinx, Microchip (RTG4), Vivado, Quartus, QuestaSim, FPGA, RTL, oscilloscopes, logic analyzers
3w
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
1mo
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Embedded FPGA Engineer
McLean, Virginia, United States
$87k-$198k/yr OnsiteFull Time
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado/Xilinx toolchains, Python/C++, MATLAB, Linux, Agile tools (Jira, Confluence); ability to obtain TS/SCI clearance; bachelor’s in EE or CE required.
Python, C++, MATLAB, Jira, Confluence, Verilog, VHDL, SystemVerilog, HLS, Vitis HLS, Vitis, Vivado, Tcl, Linux, UNIX, AXI-Stream, AXI-Lite, DMA, RTL, SDR, SOSA, VPX, GPU, Logic Analyzer, Oscilloscope, Spectrum Analyzer
2mo
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Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles
Dulles, Virginia, United States
$114k-$171k/yr OnsiteFull Time
5+ YOEBS with 5+ yrs or MS with 3+ yrs (Level 3) or PhD with 1+ yrs; SCI clearance; VHDL experience; FPGA design flow expertise; aerospace domain knowledge; leadership experience.
VHDL, RTL, Synthesis, Place and Route, Timing Analysis, Power Analysis, Vivado, QuestaSim, MATLAB, Simulink
1mo
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Front End Software Engineer
Chantilly, Virginia, United States
$78k-$176k/yr OnsiteFull Time
5+ YOE5+ years frontend development; React/TypeScript; Python/Node.js/Next.js; CSS; automated testing (Jest, RTL, Cypress, Playwright); performance optimization; WCAG/508; Git workflows; TS/SCI clearance with polygraph; Bachelor's in CS/CE or 5+ years exp (or 8+ years without degree).
React, TypeScript, JavaScript, Python, Node.js, Next.js, CSS, Jest, React Testing Library, Cypress, Playwright, Lighthouse, Git, AWS, Terraform, S3, CloudFront, Lambda, API Gateway, Tailwind CSS, Styled Components, Sass, GitHub Actions, GitLab CI
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