172 rtl engineer jobs at 52 companies in Larkspur, CA
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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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TPU RTL Design Engineer
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design experience focused on clocking/reset/timing-critical RTL,SystemVerilog and scripting (Python/Tcl/Perl) proficiency,experience with clock control and verification.
SystemVerilog, Python, Tcl, Perl
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
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Staff SoC RTL Engineer
Burlingame, California, United States
$175k-$230k/yr HybridFull Time
5+ YOEBS, MS, or Ph.D. in electrical or computer engineering; 5+ years of SoC/ASIC front-end design and integration; SystemVerilog or Verilog; computer architecture, low-power design, subsystem, and VCS experience.
SystemVerilog, Verilog, VCS, C++, FPGA
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
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RTL/Logic Design Engineer
Santa Clara or United States
$166k-$250k/yr HybridFull Time
5+ YOE5+ years digital design experience; expertise in RTL/Verilog, high-speed memory interfaces (HBM, GDDR); familiarity with Synopsys, Cadence, Mentor Graphics; strong simulation, synthesis, timing analysis skills; BS/MS in engineering.
Verilog, Synopsys, Cadence, Mentor Graphics, Register Transfer Level (RTL)
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Mixed Signal RTL Design Engineer
Sunnyvale, California, United States
OnsiteFull Time
Specify, design, verify, and assist lab bring-up of advanced mixed-signal circuits (digital side).
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Micro-Architect and RTL Designer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
4+ YOE4+ years micro-architecture and RTL design experience; SystemVerilog, Python, C/C++; ASIC/SoC concept-to-silicon experience; synthesis and sign-off flows; verification collaboration; US work authorization and export-control compliance.
SystemVerilog, Python, C/C++
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
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Senior Electrical Engineer - Sensor FPGA and PCB (Aggregator)
Sunnyvale or Austin
$170k-$195k/yr OnsiteFull Time
5+ YOERequires 5+ years in electrical engineering, FPGA hardware and RTL development, high-speed mixed-signal design, debugging, and a Bachelor's, Master's, or PhD in electrical engineering or a related field.
FPGA, VHDL, Verilog, CSI-2, GMSL2, FPD-Link, 10GbE, RTL, Ethernet, PCIe, Vivado, Quartus, Lattice Radiant, ModelSim, Questa, MIPI CSI-2, PLM, SerDes, ISP, PHY
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ASIC Engineer, Design
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years hardware design experience for production silicon,expertise in microarchitecture,RTL and SoC integration,strong communication and collaboration skills.
RTL, Synthesis, Timing Closure, Formal Verification Methodology, SoC, EMR
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
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Senior FPGA Engineer, LEO Payload FPGA
Sunnyvale, California, United States
$183k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in Electrical Engineering, 7+ years FPGA/System Verilog experience, proficiency with ASIC/FPGA tools, Python test scripting, Xilinx/AMD/Altera FPGAs, RTL/uArchitecture, timing and power optimization, simulation and validation.
System Verilog, Python, Xilinx, AMD, Altera, uArchitecture, RTL, Cocotb, AXI4, AXI Streaming, SerDes, Interlaken, 50G/100G Ethernet
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Staff Silicon Validation Engineer
Palo Alto, California, United States
$186k-$232k/yr OnsiteFull Time
Bachelor's degree in EE/CSE or related, proficiency in C/C++, Python and Linux shell, experience with SoC/FPGA validation preferred (AMD Petalinux, RTL), strong analytical and communication skills.
C, C++, Python, Linux shell, AMD Petalinux, FPGA, RTL
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FPGA Engineer
Sunnyvale or United States
$150k-$220k/yr RemoteFull Time
Bachelor's or master's degree in computer or electrical engineering; expertise with System Verilog, Xilinx FPGAs, Vivado, RTL verification, AXI, timing analysis, and FPGA platforms.
SystemVerilog, Xilinx, AMD, Vivado, ILA, C, C++, Xilinx Versal, Xilinx Alveo, QSFP+, GTY, GTM, AXI
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Software Engineer - FPGA-Accelerated RTL Simulation
Berkeley, California, United States
$179k-$219k/yr OnsiteFull Time
7+ YOEBS, MS, or PhD in CS, CE, or EE; 7+ years building complete modern C++ applications; strong C++ concurrency and multithreaded application experience; strong oral and written communication.
C++, C++20, Chisel, Xilinx FPGAs, MLIR, CIRCT, LLVM, RISC-V, FireSim
3d
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Principal Verification Engineer
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOERequires a degree in electrical engineering, computer engineering, computer science, or related field and 3–8+ years of technical engineering experience depending on degree; verification, UVM, RTL, simulation, scripting, and security screening required.
Universal Verification Methodology (UVM), C, Zsh, Bash, Python, Perl, Verilog, Microsoft Azure, AXI, AMBA
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