211 asic engineer jobs at 51 companies in Larkspur, CA
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
2d
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ASIC Design Engineer
Alameda, California, United States
$100k-$140k/yr OnsiteFull Time
Bachelor's in Electrical Engineering or Computer Science with ASIC industry experience, or Master's/PhD with hands-on ASIC experience. Requires analog and RTL design, programming, testing, debugging, communication, and Linux experience.
Linux, SPI, I2C, Cadence, Raspberry Pi, PDKs
2w
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and experience with test planning, coverage, assertions, simulation, and waveform debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
2w
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, SystemVerilog and UVM expertise, test planning, coverage analysis, assertions, randomization, and simulation-tool proficiency.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
2w
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and proficiency with test planning, coverage, assertions, randomization, and simulation debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
2w
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Mid Level ASIC Design Engineer
Sunnyvale or Munich
OnsiteFull Time
3+ YOERequires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog, CPU IP integration, processor architecture and interface knowledge, front-end ASIC tools, low-power design, and a bachelor's degree in electrical or computer engineering.
Verilog, SystemVerilog, ARM, RISC-V, MIPS, AMBA, APB, AXI, SPI, eMMC, MII, GPIO, I2C, UPF
1w
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
1w
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
3mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
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ASIC Formal Verification Engineer, TPU Compute
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical/Computer Engineering or Computer Science; 8 years in silicon/ASIC/SoC design; experience with SystemVerilog Assertions and formal verification.
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Principal Analog/Mixed-Signal ASIC Engineer
Sunnyvale, California, United States
$258k-$294k/yr HybridFull Time
10+ YOEPh.D. in EE or related field, 10+ years ASIC AMS and/or high-speed design experience, leading ASIC tape-outs, top-level ASIC architecture ownership, DRC/LVS/PI/SI verification experience, strong communication.
Register-Transfer Level (RTL), SOS, Git, Calibre
2d
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Sr ASIC Physical Design Engineer
Sunnyvale, California, United States
$371k/yr HybridFull Time
5+ YOEBachelor’s degree plus 7 years of related experience or master’s degree plus 5 years; 5 years in ASIC physical design, CMOS, EDA tools, scripting, STA, Verilog HDL, and advanced process technologies.
Cadence Innovus, Synopsys IC Compiler, Mentor Graphics Olympus, TCL, Perl, Python, Verilog HDL, CMOS, TSMC 5nm, TSMC 3nm
3mo
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Senior ASIC Design Engineer
Santa Clara, California, United States
$136k-$219k/yr HybridFull Time
3+ YOEBS in Electrical or Computer Engineering; 3+ years in logic design (Verilog/SystemVerilog); experience with clock domains, digital systems, and VLSI; Python/Perl programming; strong communication skills.
Verilog, SystemVerilog, Python, Perl
2mo
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ASIC Design Engineer (eInfochips)
Mountain View, California, United States
OnsiteFull Time
5+ YOE5+ years Verilog/SystemVerilog design; Fusion Compiler experience; scripting; PCIe and AXI interfaces; ARM Fabric IP; IPXACT; EDA tools.
Fusion Compiler, VCS, Questa CDC, Spyglass Lint, Design Compiler, Genus, UPF, Python, Tcl, Perl, Verilog, SystemVerilog, AXI, AMBA, IPXACT
2w
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ASIC III - AMZ10291241
Sunnyvale, California, United States
$237k-$248k/yr OnsiteFull Time
5+ YOEMaster's and 5 years' experience, or bachelor's and 7 years' progressive experience, in computer science, engineering, or related field. Requires 5 years with STA, Tcl/Perl/Python automation, physical design flows, and SoC design.
Tcl, Perl, Python, Static Timing Analysis (STA), LSF, RTL, SoC
3mo
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SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
BS or MS in Electrical/Computer Engineering; experience with ASIC/RTL design; knowledge of Ethernet, SerDes, and high-speed I/O; scripting (Perl/Python/Shell); experience with SystemVerilog/Verilog; VCS; strong communication and problem-solving skills.
VCS, SystemVerilog, Verilog, Perl, Python, Shell, RTL design, SerDes
3mo
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Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
2mo
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ASIC Architect
Sunnyvale, California, United States
OnsiteFull Time
10+ YOEMasters or PhD in Electrical/Computer Engineering; 10+ years performance analysis and modeling experience across GPUs/CPUs/accelerators; strong computer architecture background; ability to build performance models in Python.
Python
3d
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ASIC Package SI/PI Engineer
San Francisco, California, United States
$266k-$445k/yr HybridFull Time
5+ YOERequires 5+ years in signal integrity, power integrity, high-speed interconnects, PDN, and package electrical design, plus SI/PI simulation, package layout, and automated optimization experience.
Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI, Sigrity PowerDC, Cadence APD/SIP, VNA, TDR/TDT
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