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153 asic engineer jobs at 19 companies in Oceanside, CA

3mo
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ASIC Design Engineer
Irvine or Andover
$108k-$173k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
6+ YOEBachelor's in Electrical Engineering with 8+ years of related experience or Master's in Electrical Engineering with 6+ years of related experience; ASIC implementation, synthesis, DFT, floorplanning, place & route, clocking, power planning and analysis, timing closure, signal integrity, physical design checks.
EDA tools, Synthesis tools, Place and Route (P&R) tools, Floorplanning tools, Clocking/Timing analysis tools, Power analysis tools
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3w
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ASIC Methodology Engineer
Santa Clara or San Diego
$153k-$230k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
3+ YOEMS/PhD or BS with experience in ASIC/VLSI design flows; strong Python skills; hands-on STA experience with PrimeTime or Tempus; problem-solving and analytics; version control experience preferred.
Python, PrimeTime, Tempus, Perforce, Git, GPT, Liama
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1mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
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Sr Principal ASIC Design Engineer - Terawave
San Diego or California or Austin or Texas or Kent
$308k-$431k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
15+ YOEExperienced ASIC/SoC design and verification engineer with expertise in Verilog/SystemVerilog, DSP structures, ARM integration, interface protocols, FPGA flows, post-silicon bring-up; BS/MS in EE or related and 15+ years experience required.
Verilog, SystemVerilog, MATLAB, SystemC, C
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4w
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
Boeing
BoeingNYSE: BA: Designs and manufactures aircraft, defense systems, and space technology.
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
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2mo
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ASIC/FPGA Verification Engineer - (Associate, Experienced, or Lead) - SoCal
El Segundo or Huntington Beach
OnsiteFull Time
Boeing
BoeingNYSE: BA: Designing and manufacturing commercial aircraft and defense systems.
5+ YOEBachelor's degree in engineering or related field; experience in ASIC/FPGA verification; SystemVerilog/UVM; HDL proficiency; testbenches, coverage models, and regression testing experience.
SystemVerilog, UVM, HDL, Verilog, Python, Make, Perl, Git, SV Assertions
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1mo
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ASIC Design Engineer I, Satellite Communications
San Diego, California, United States
$123k-$170k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
2+ YOEBachelor's in Electrical Engineering; 2+ years in digital logic/DSP design; RTL implementation; DSP algorithms optimization.
MATLAB, RTL, UVM, SystemC, DPI-C, Verilog, VHDL
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2mo
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Senior Principal Engineer Digital ASIC Design/Manager
San Diego, California, United States
$214k-$348k/yr OnsiteFull Time
Kyocera
KyoceraTokyo Stock Exchange: 6971: Manufactures advanced ceramic components and high-tech electronic equipment.
15+ YOEBS or MS in Electrical Engineering; 15 years in Digital ASIC design; leadership; cross-functional collaboration; RTL/verification; experience with mixed-signal interfaces is a plus.
Verilog, SystemVerilog, LINT, LEC, RDC/CDC, SDF, Genus, Conformal, Innovus, Spyglass Lint, TetraMax, Xcelium, Cadence, Synopsys PrimeTime, VCS, UGV, UVM
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3mo
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Cellular ASIC Design Engineer
Austin or San Diego or Sunnyvale
HybridFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
10+ YOEBS degree and 10+ years of industry experience in VLSI; hands-on RTL to GDSII flows; experience optimizing power, performance, area and cost for SoCs; exposure to design technology co-optimization and early tech node analysis.
RTL to GDSII flows, Synthesis tools (DC/DCT/DCG/Genus/Oasis), P&R tools (ICC2/Fusion/Innovus/Aprisa), signoff tools (PT/PT-SI/Tempus), Power signoff tools (RedHawk/SeaHawk/Voltus), SPICE simulators (Hspice/Finesim/AFS/Spectre/Infinisim), EDA tooling automation (Python, Perl, TCL, Unix shell, C/C++), ML analytics tools, STA methodologies
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1w
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ASIC/FPGA Verification Engineer - (Associate, Experienced, or Lead) - SoCal
El Segundo or Huntington Beach
$86k-$171k/yr OnsiteFull Time
Boeing
BoeingNYSE: BA: Designs and manufactures commercial airplanes, defense systems, and space technology.
2+ YOEBachelor's degree or equivalent, ASIC/FPGA verification experience using SystemVerilog/UVM, coverage and regression development, testbench design, revision control (svn/cvs/git), and Linux proficiency.
UVM, SystemVerilog, SystemVerilog Assertions, svn, cvs, git, Linux, Palladium, Make, Perl, Python, JESD204C, PCIe, Ethernet
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Principal Engineer, ASIC/VLSI Synthesis and Design
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
5+ YOE10-15 years in ASIC implementation and synthesis; strong RTL-to-GDSII flow; experience with UPF, ECOs, STA; 5-10 years on advanced nodes; scripting.
Fusion Compiler, Conformal ECO, Conformal Low Power, UPF, Scripting (Tcl, Python)
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3mo
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ASIC Design Verification Engineer (All Levels)
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
Marvell Technology
Marvell TechnologyNASDAQ: MRVL: Developing semiconductor solutions for cloud, enterprise, and AI infrastructure.
4+ YOEBS/ MS/ PhD with 2-10+ years verification experience; SystemVerilog/UVM; test planning and coverage; Python/Perl; Linux; C++/ARM; networking knowledge a plus.
SystemVerilog, UVM, Python, Perl, EDA tools, Linux, C++, ARM assembly
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ASIC Design Verification Technical Leader
Carlsbad or Allentown
$164k-$235k/yr OnsiteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
8+ YOEBachelor's or higher in Electrical/Computer Engineering; 8+ years ASIC design verification or 6+ with masters; strong SystemVerilog/UVM; leadership experience; scripting (Python, Perl, TCL, Shell).
SystemVerilog, UVM, Python, Perl, TCL, Shell
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1mo
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Electrical Engineer, ASIC Program Lead-CA
San Diego, California, United States
$160k-$200k/yr OnsiteFull Time
Synchron
Synchron: Developing implantable brain-computer interfaces to restore functional independence.
12+ YOE12+ years experience with end-to-end custom ASIC/SoC development, mixed-signal and analog front-end expertise, strong digital design and verification experience, EE degree (BS required, MS preferred), lab debugging skills, and cross-functional collaboration.
Verilog, VHDL, SystemVerilog, UVM, EDA tools, Python, MATLAB, C/C++, Tcl, oscilloscopes, logic analyzers, spectrum analyzers, signal generators, precision measurement equipment, custom test fixtures
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1w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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2mo
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Principal Analog Design Engineer
San Diego, California, United States
$175k-$240k/yr OnsiteFull Time
Elevate Semiconductor
Elevate Semiconductor: Designs integrated circuits for automated semiconductor test equipment.
20+ YOE5+ MgmtMaster’s or PhD in Electrical Engineering; 20+ years MSEE or 15+ years PhD in analog/mixed-signal IC design; leadership in analog ASICs; high-voltage analog design; MATLAB/Simulink/Verilog-A modeling; cross-functional collaboration.
MATLAB, Simulink, Verilog-A, Octave
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4d
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
InnoPhase
InnoPhase: Designing energy-efficient semiconductor solutions for 5G cellular networks.
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
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FPGA Verification Engineer, Air Vehicles
Costa Mesa, California, United States
$123k-$171k/yr OnsiteFull Time
Anduril Industries
Anduril Industries: Defense technology building autonomous military hardware and software.
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog, UVM, SVA, industry simulators, Git, Linux; eligible to obtain U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, Python, Tcl, Makefile, SVUnit, Nix
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GPU Design Verification Engineer
San Diego, California, United States
$180k-$301k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
10+ YOEMS/PhD or equivalent,10+ years ASIC design verification experience,SystemVerilog/UVM,constrained random,functional coverage,hw/sw co-simulation,emulation,strong debugging and GPU architecture knowledge.
SystemVerilog, UVM, emulation
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FPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)
Costa Mesa, California, United States
RemoteFull Time
Hikinex
Hikinex: Provider of outsourced sales and administrative business solutions.
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog/UVM/SVA, experience with industry simulators, Git and Linux, eligible for U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Nix
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