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CPU Systems RTL Engineer
Santa Clara, California, United States
$167k-$251k/yr OnsiteFull Time
5+ YOEMS in Computer/Electrical Engineering with 5+ years CPU RTL experience; strong microarchitecture knowledge; Verilog or VHDL experience; familiarity with timing, power, and simulators; scripting with Perl or Python.
Verilog, VHDL, Perl, Python
1w
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RTL Design Engineer
San Jose, California, United States
HybridFull Time
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
1mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
1mo
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
1mo
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Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
3mo
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Senior RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$159k-$194k/yr OnsiteFull Time
3+ YOE3+ years of RTL design experience; Verilog/SystemVerilog/VHDL; CPU RTL design; Chisel/Scala experience a plus; strong software engineering skills.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, Jira, Confluence
3mo
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CPU Microarchitect/RTL Engineer
Santa Clara, California, United States
OnsiteFull Time
BS degree; Verilog or VHDL experience; preferred CPU microarchitecture, RTL, C/C++, Python/Perl.
Verilog, VHDL, C, C++, Python, Perl
2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
1w
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
1mo
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
1mo
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Sr. RTL Design Engineer (Silicon Engineering)
Irvine or Austin or Redmond or Sunnyvale
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS; 5+ years RTL implementation; Verilog/SystemVerilog; ASIC/SoC integration; clock domain crossing; scripting and EDA tools.
Verilog, SystemVerilog, HDL simulators, HDL Lint tools, Python, EDA tools, Scripting, AXI, AHB
1mo
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
1mo
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Senior Principal Engineer, Micro-architecture and RTL
Santa Clara, California, United States
$182k-$273k/yr OnsiteFull Time
15+ YOEBachelor's in CS/EE with 15+ yrs; MS with 10-12 yrs; PhD with 8-10 yrs. SystemVerilog RTL, UVM, Ethernet, PCIe, CXL experience; leadership ability.
SystemVerilog, SystemVerilog Assertions, Universal Verification Methodology, RTL, PCIe, CXL, Ethernet
1mo
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Staff System Software Engineer, RTL-to-GDS Flow Platform
Santa Clara, California, United States
$184k-$357k/yr OnsiteFull Time
12+ YOEB.S./M.S. in CS/EE/CE or equivalent experience; 12+ years building or operating production EDA/VLSI CAD or RTL-to-GDS workflow systems; strong Tcl and Make experience; software skills in Python, Perl, Go, or C++; excellent Linux debugging and configuration expertise.
Tcl, Make, Perl, YAML, Python, Go, C++, Linux, LSF, Slurm, Grid Engine, NFS
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign engineer with strong Verilog/SystemVerilog, ASIC design, RTL timing and verification experience.
Verilog, SystemVerilog, RTL, EDA tools, Python, Perl
2mo
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Quality Engineer
Santa Clara, California, United States
$120k-$125k/yr OnsiteFull Time
Master’s degree in Electrical or Computer Engineering or related field; strong background in digital IC design, IC fabrication, C, RTL, VHDL/Verilog, semiconductor physics, reliability prediction.
MATLAB, Visual C, Excel, pFA, eFA, SEM, OBIRCH, X-ray analysis, Oscilloscope, C programming, RTL design, Verilog, VHDL, IC fabrication, Reliability prediction
2mo
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Staff Design Engineer
San Jose, California, United States
$145k-$246k/yr OnsiteFull Time
7+ YOEBachelor's in Computer or Electrical Engineering; 7+ years digital circuit design; RTL and gate-level verification; collaboration across multi-functional teams.
RTL, Verilog, Gate-level verification
1w
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Senior Design Engineer
San Jose, California, United States
$116k-$198k/yr OnsiteFull Time
5+ YOEBachelor's in Computer or Electrical Engineering,5+ years digital circuit design experience,RTL and gate-level verification,Verilog proficiency,ability to meet performance/area/power targets.
RTL, Verilog, AI tools
1w
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DFT Methodology Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
10+ YOE10+ years SoC/DFT experience, Master's in Electrical Engineering or equivalent experience, strong RTL/verification and silicon bring-up skills, knowledge of DFT architectures and security.
I1149.1, I1500, I1687, 1838, memory BIST, RTL, STA, place-n-route, ATE, pattern generation, Verification
3w
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Product Development Engineer
San Jose, California, United States
$106k-$154k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in Electrical Engineering (or related) with 5+ years industry experience in IC design/test, DFT/ATPG/MBIST/IJTAG/JTAG, RTL design/synthesis/verification, scripting (Python/Perl/TCL), and semiconductor manufacturing test.
Python, Perl, TCL, ATPG, MBIST, IJTAG, JTAG, RTL, Secure Device Manager (SDM)
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