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Digital Design Engineer
San Jose, California, United States
$130k-$200k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in EE/CE,5+ years digital RTL design experience,SystemVerilog proficiency,ASIC flow and EDA tool experience,high-speed SerDes/DSP knowledge,Python/MATLAB/C++ familiarity.
System Verilog, Synopsys, Cadence, Siemens, Python, MATLAB, C++
1mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
4w
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
2mo
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Principal Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
5+ YOEBachelor’s or Master’s in Electrical/Computer Engineering or related field; 5-10 years in digital design for high-speed DSP data paths; SystemVerilog coding; experience with Synthesis, Lint, CDC, PrimeTime; RTL delivery; full design cycle; timing/area/power optimization; silicon issue resolution
SystemVerilog, EDA tools, Synthesis, Lint, CDC, PrimeTime
2h
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Senior HSIO Digital Design Engineer
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
3+ YOE3+ years industry experience in digital HSIO or die-to-die interfaces; BS/MS/PhD in Electrical Engineering with specified experience; knowledge of high-speed serial protocols, SI/PI, and digital/analog co-design.
AXI, CHI, CXS.B, CXL, PCIE, UA-Link
1mo
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Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
1w
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
1mo
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Technical Staff Engineer - Digital Design
San Jose, California, United States
$70k-$143k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12+ years relevant experience (10+ in FPGA/ASIC IP and system design), VHDL/Verilog expertise, FPGA design/verification experience, strong digital design and architecture knowledge, excellent communication; US citizenship or permanent residency required.
VHDL, Verilog, Libero, Quartus, Vivado, Identify Debugger, SignalTap, ChipScope, ModelSim, QuestaSim, Python, TCL
2mo
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Digital Design Engineer - New College Grad
San Jose, California, United States
$99k-$183k/yr HybridFull Time
Master's degree in EE or related field; experience with RTL coding, Verilog models, and analog/digital design; test support and chip bring-up; strong communication and team skills.
Verilog, RTL, Simulations, I2C, SPI, AHB, APB, Bench testing, ATE testing
1w
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
1w
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Principal Digital Design Engineer
San Jose, California, United States
$190k-$240k/yr HybridFull Time
8+ YOEMS/PhD EE with 8+ years or BS EE with 12+ years; SOC architecture experience, bus/interface protocols, embedded memory knowledge, RTL/DFT/synthesis flow, silicon bring-up, strong communication and team skills.
AHB, APB, AXI, USB, I2C, I3C, SPI, UART, SRAM, OTP, MTP, EE/Flash, DDR DRAM, Flash
1mo
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
1w
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Distinguished Engineer, Digital IC Design
Santa Clara, California, United States
$210k-$314k/yr OnsiteFull Time
15+ YOEMaster's required (Ph.D. preferred),15+ years experience in uLED/uVCSEL, ASIC architecture, chiplet and multi-die design, demonstrated leadership, patents/publications, system integration expertise.
1w
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Senior Staff Engineer, Digital IC Design
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEDegree in computer or electrical engineering with 3–5+ years SOC/SoC experience, RTL design in SystemVerilog, SoC integration and timing closure, CDC/clock/reset design, and scripting with Python or Tcl.
SystemVerilog, Python, Tcl
3w
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SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS or related, 1+ years front-end digital design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile).
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA, FPGA, ASIC
1mo
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
2w
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Sr. / Staff ASIC Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
6+ YOEExpertise in DFT, synthesis, power and timing analysis; tapeout experience; scripting (tcl/perl/python/shell); UPF and STA; Bachelors+8 years or Masters+6 years in engineering.
Synopsys, Siemens Tessent, PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, UPF, UNIX, Linux, tcl, perl, python, shell
3w
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Design Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in Electrical/Computer Engineering (or equivalent), 3+ years SystemVerilog RTL design experience, strong digital design fundamentals, power/timing-aware practices, simulation debug, and scripting in Python/Perl/TCL.
SystemVerilog, Python, Perl, TCL, UVM, SVA
1mo
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Principal Design Engineer
San Jose, California, United States
$198k-$336k/yr OnsiteFull Time
10+ YOEMS in Electrical Engineering or equivalent with 10+ years ASIC design experience; expertise in Verilog/SystemVerilog; knowledge of full digital ASIC design flow; experience with Design Compiler and PrimeTime; Python and AI-assisted tool familiarity.
Verilog, SystemVerilog, Design Compiler, PrimeTime, ncsim, Formality, Python
1w
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Senior Digital Product Designer, Design Systems
Milpitas, California, United States
$121k-$206k/yr HybridFull Time
6+ YOE6+ years product design with 2+ years in design systems, expertise in design tokens/component architecture, accessibility-first approach, experience partnering with engineers, advanced Figma skills, Bachelor's in design/HCI or related.
Figma
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