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20 rtl engineer jobs at 6 companies in West Sacramento, CA

2w
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HBM SoC RTL Design Engineer
Folsom, California, United States
$121k-$247k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
3+ YOE3+ years SoC/RTL design experience, proficiency in SystemVerilog/Verilog, RTL-to-GDS flow knowledge, familiarity with EDA toolchains, scripting (Python/TCL/Perl/shell), and SoC integration skills.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, shell, Palladium, Veloce, Zebu
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3mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
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1mo
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
Solidigm
Solidigm: Develops and manufactures NAND flash memory and solid-state drives.
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
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1w
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Principal Engineer - Design
Roseville, California, United States
$75k-$232k/yr OnsiteFull Time
Microchip Technology
Microchip TechnologyNasdaq: MCHP: Manufacturer of microcontrollers, analog, and mixed-signal integrated circuits.
10+ YOE10+ years experience in SoC design/verification, BS/MS in Electrical/Computer Engineering, experience with serial protocols (SAS/SATA/NVMe, PCIe), Linux and C/Python scripting, RTL (VHDL/Verilog/System Verilog).
Cadence Palladium, Protium, Linux, C, Python, Tcl, Bash, VHDL, Verilog, System Verilog, JTAG, I2C
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4d
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
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3mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
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2mo
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Mixed Signal Logic Design Engineer
Folsom or San Jose or Santa Clara
$122k-$232k/yr OnsiteFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
4+ YOEBachelor's with 4+ years or Master's with 3+ years or PhD with 1+ year in CS/CE/EE; 2+ years RTL design SystemVerilog/Verilog; mixed-signal, UPF, clock gating; VCS/Verdi; FE tools; no visa sponsorship.
SystemVerilog, Verilog, VCS, Verdi, UPF, Lint, CDC, RDC, Synthesis, Voltage Domain Crossings, DDR, LPDDR, VSCode, Git
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6d
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Director, ASIC Design & Front-End Implementation
Roseville, California, United States
OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
15+ YOE8+ MgmtBS/MS in electrical or computer engineering, 15+ years ASIC development experience, 8+ years leading engineering teams and managers, and expertise in RTL, Verilog/SystemVerilog, microarchitecture, synthesis, CDC, linting, timing closure, and ASIC flows.
Verilog, SystemVerilog, CI/CD
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