3mo
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RTL Design Engineer
Austin, Texas, United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience with RTL design, Verilog/SystemVerilog, DSP, and mixed-signal/analog integration.
Verilog, SystemVerilog, DSP, Scripting (Python, Perl), Synthesis, Verification, DFT, Lint tools
3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
3w
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
3w
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CPU Core RTL Design Engineer
Austin, Texas, United States
HybridFull Time
Design and implement CPU core RTL, contribute to microarchitecture, collaborate with verification and physical design, and debug pre/post-silicon issues; Bachelor’s+ in EE/CE preferred.
Verilog, SystemVerilog, Python, Tcl
2d
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
2d
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ASIC SoC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in SoC/IP/Subsystem verification, SystemC/TLM and RTL verification, hardware emulation familiarity, strong problem-solving and communication; BS required (MS preferred).
SystemC, TLM, RTL, hardware emulation
1mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr OnsiteFull Time
3+ YOE3+ years relevant experience, Bachelor's/Master's in Computer or Electrical Engineering (or equivalent), proficiency in System Verilog, UVM, Python, Verilog, RTL, and familiarity with VCS and Verdi.
System Verilog, UVM, Python, Verilog, RTL, VCS, Verdi
1mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
2mo
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Principal Design Verification Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or CS; 10+ years in design verification/test benches; UVM/OVM/VMM; RTL design; Python scripting; open to extended hours.
UVM, OVM, VMM, Python, RTL design
3mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
1mo
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Staff RTL Design Engineer - CPU LS/PF/MMU
Santa Clara or Austin
$179k-$219k/yr OnsiteFull Time
3+ YOEBS/MS in CS/CE/EE or equivalent, 3+ years design experience, CPU RTL design experience, proficiency in Verilog/System Verilog/VHDL, strong software engineering (OOP, functional, TDD), verification skills (SVA, coverage).
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, RISC-V, Git/Github, Jira, Confluence, SVA
1mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
1mo
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Senior Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS required, 4+ years IP/SoC design or verification experience, Verilog/SystemVerilog/UVM skills, SVA and verification (test planning, simulation, debug), familiarity with Python, C/C++, Perl, TCL and AI/ML tools; ARM AMBA knowledge a plus.
Verilog, SystemVerilog, UVM, System Verilog Assertion (SVA), Python, C/C++, Perl, TCL, Makefiles, AI/ML tools, ARM AMBA, RTL
3mo
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Design Verification Engineer - Interface IP
Austin or San Jose
$150k-$275k/yr OnsiteFull Time
5+ YOE5+ years in design verification; SystemVerilog/UVM; experience with IP interfaces (PCIe, Ethernet, AXI/AMBA, ARM/ARC); able to collaborate across RTL, software, and emulation; thrives in a fast-paced startup.
SystemVerilog, UVM, PCIe, Ethernet, AXI/AMBA, ARM/ARC CPUs
2d
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$114k-$172k/yr OnsiteFull Time
2+ YOEBachelor's in CS/CE or equivalent,2+ years SystemVerilog/UVM or C/C++ hardware verification, experience with EDA simulation tools and scripting (Python,TCL,Perl,Shell),and RTL debug/root-cause analysis.
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, EDA simulation tools, Emulation
1mo
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Senior Application Engineer - Design Verification
Austin, Texas, United States
HybridFull Time
3+ YOEBachelor's or Master's in EE/CE (or related) with 3+ years experience; hands-on DV flow development; SystemVerilog/UVM; advanced testbench and flow automation; RTL and gate-level debugging; strong customer-facing and problem-solving skills.
SystemVerilog, UVM, EDA tools, proteanTecs DV flow
4d
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Sr. Formal Verification Engineer, Annapurna Labs
Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/EE,7+ years formal verification experience as IP/block owner, expertise in abstraction and end-to-end checking, RTL and microarchitecture comprehension, and coding/scripting skills.
C, C++, C#, Node.JS, Java, Python, PHP, Ruby
2mo
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CPU Core Design Verification Testbench Lead
Austin or Santa Clara
HybridFull Time
8+ YOE8+ years in CPU verification and testbench development; deep hands-on experience with high-performance out-of-order RISC-V cores; CVM/UVM experience; cross-functional debug across RTL, logs, and post-silicon environments; familiarity with AI-assisted verification.
CVM, UVM, Python, C/C++
1d
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R&D Engineer IC Design 4
Austin or San Jose
$122k-$195k/yr OnsiteFull Time
6+ YOEDesign and verify RTL/Verilog blocks for ASICs including synthesis, timing closure, formal verification, scripting, and RTL/gate-level power analysis. BS/MS in ECE and 6+ years experience.
Verilog, RTL, TCL, Perl, Synopsys Design Compiler, DC topo, Cadence RTL Compiler, Primetime, liberty (LIB), Synopsys Formality, Cadence Conformal, Spyglass, svn, git
1mo
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Firmware Engineer II
Austin, Texas, United States
OnsiteFull Time
Develop bare-metal firmware in C for DDR5 PHY and microcontrollers; debug RTL simulations and silicon bring-up; knowledge of DDR5 JEDEC spec, scripting (Shell/Perl/Python/TCL), and verification EDA tools required.
C, Verilog, microcontrollers, Shell, Perl, Python, TCL, IDE, RTL, simulators, waveform viewers, Verification EDA Tools