2mo
Save
Mark Applied
Hide
SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
Master’s in Electrical or Computer Engineering; ASIC/SoC design experience; RTL/verification; EDA tools; programming (Python/C++/Perl).
Verilog, SystemVerilog, PrimeTime, Cadence Virtuoso, Design Compiler, Simvision, Python, C++, Perl, SVA, HLS, EDA Tools
1mo
Save
Mark Applied
Hide
Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
2mo
Save
Mark Applied
Hide
Wireless SoC Design Engineer
San Diego or Sunnyvale
OnsiteFull Time
Bachelor's degree in Electrical Engineering or Computer Engineering; experience with ASIC/SoC RTL design; SystemVerilog; cross-functional collaboration.
SystemVerilog, SystemVerilog RTL, Synthesis, STA, Lint, CDC, RDC, DFT, DFT, PCIe, QSPI, UART, SPMI
1mo
Save
Mark Applied
Hide
SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
3w
Save
Mark Applied
Hide
SOC IP Methodology Engineer - Custom SOC
Santa Clara or Austin or Hillsboro
$168k-$311k/yr OnsiteFull Time
8+ YOEMasters (8+ yrs) or BS (10+ yrs) with deep RTL-to-GDS methodology and physical design expertise, experience with EDA tool flows, IP ecosystems, customer-facing SOC development, DFT/BIST, synthesis/CTS/power/PNR, and scripting (Python/Perl/Tcl).
RTL-to-GDSII, Cadence, Synopsys, Mentor, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT-SI, Tempus, Redhawk, IP-XACT, Python, Perl, Tcl
3w
Save
Mark Applied
Hide
SoC Logic Design Engineer
Hillsboro or Santa Clara or Austin
$142k-$200k/yr HybridFull Time
3+ YOEDegree in electrical/computer engineering (BS+4 yrs / MS+3 yrs / PhD+6 mo) and experience in RTL/SystemVerilog, SoC logic integration, microarchitecture, timing/power convergence, and simulation; scripting and front-end RTL tools preferred.
Register Transfer Level (RTL), System Verilog, Python, Perl, Lint, CDC, Synthesis, Static Timing Analysis (STA), DFT, DFD, UVM
3mo
Save
Mark Applied
Hide
SOC Architect
Santa Clara or Cambridge or France or Oregon or Boston
$254k-$311k/yr OnsiteFull Time
10+ YOEMS or PhD in Computer Science / Computer Architecture; 10+ years in SoC architecture; 5+ years in engineering teams; experience in SoC design flow, architecture, and performance modeling; CPU architectures, power management, platform hardware, OS, drivers, and firmware.
1mo
Save
Mark Applied
Hide
Sr. Principal Engineer, SoC Architect
San Jose, California, United States
$250k-$304k/yr OnsiteFull Time
15+ YOE15+ years in SoC/system architecture; strong high-speed I/O and interconnect knowledge; leadership, cross-functional collaboration.
PCIe, PCIe Gen5, PCIe Gen6, CXL/UCIe, HBM, SerDes, Ethernet, USB, Memory interconnect, Interconnect
2mo
Save
Mark Applied
Hide
SoC Architect
San Jose or United States
$175k-$350k/yr HybridFull Time
18+ YOEBachelor's/Master's/PhD in EE/Computer Engineering or related; 18+ years in SoC/system architecture; expertise in high-speed IO, data movement, performance modeling, and cross-functional collaboration.
UCIe, PCIe, CXL, UALink, ESUN, Ethernet
3w
Save
Mark Applied
Hide
SoC Architect
Santa Clara, California, United States
$175k-$265k/yr HybridFull Time
d-Matrix: Develops high-performance semiconductor chips for generative AI inference.
5+ YOEMS in CS/ECE or related with 5+ years in SoC/compute architecture; expert in AI SoC architecture, performance modeling, ML (transformer/CNN/RNN), workload analysis; strong Python; C/C++ preferred; leadership in architecture delivery.
Python, C, C++
2mo
Save
Mark Applied
Hide
Senior Staff SoC Design Engineer
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEBachelor's in CS/EE with 5-10 years; or Master's/PhD with 3-5 years; strong SystemVerilog RTL; SoC integration; AMBA AXI; scripting (Python/Tcl).
SystemVerilog, AMBA AXI, Python, Tcl, Synthesis, CDC/RDC, UCIe, UALink
2d
Save
Mark Applied
Hide
SOC Verification and Methodology Engineer - SCL
Santa Clara, California, United States
$153k-$230k/yr OnsiteFull Time
2+ YOEDevelop and implement SOC verification methodologies, create and execute test plans, debug issues; requires SystemVerilog/UVM experience and design verification background.
SystemVerilog, UVM, Perl, Python
3mo
Save
Mark Applied
Hide
Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
1w
Save
Mark Applied
Hide
SoC Digital Verification Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in a related field,1+ years ASIC/SoC verification experience,mastery of SystemVerilog and UVM,proficiency with simulation/debug tools and Python/Perl/Shell scripting.
SystemVerilog, UVM, VCS, Incisive, Questa, Verdi, Python, Perl, Shell, Palladium, ZeBu, JasperGold, FPGA, ASIC
2mo
Save
Mark Applied
Hide
Staff/Principal Engineer - Design Verification (SoC expert/lead)
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
10+ YOE10+ years SoC verification; SystemVerilog/UVM; PCIe/NVMe/NAND/DDR; emulation; Gen-AI tools; leadership in verification
SystemVerilog, UVM, PCIe, NVMe, NAND, DDR, emulation, Gen-AI tools
1mo
Save
Mark Applied
Hide
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Austin or Irvine or Sunnyvale
$170k-$230k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical, computer engineering or computer science; 5+ years ASIC/physical design flow development; strong RTL2GDSII, EDA tools; DFT/MBIST; scripting (Python, TCL, Perl, Bash).
RTL2GDSII, EDA tools, Python, TCL, Perl, Bash, Makefile
3mo
Save
Mark Applied
Hide
SoC Performance Architect
San Jose, California, United States
$208k/yr OnsiteFull Time
7+ YOE7+ years with Bachelor's in CS/Engineering or 5+ with Master, or 3+ with PhD; strong modeling/analysis skills; C/C++, Python; CPU/GPU/memory subsystems experience; gem5 preferred.
C, C++, Python, gem5, CPU, GPU, memory subsystems
2mo
Save
Mark Applied
Hide
Sr. Principal SoC Architect (AI2501)
San Jose, California, United States
$231k-$358k/yr OnsiteFull Time
20+ YOEMS or PhD in EE/CS, 20+ years developing hardware-focused products, 3+ years architecting and tape-out of complex ML SoCs, strong ML/math foundation, HW/SW co-design and industry/publication experience.
2mo
Save
Mark Applied
Hide
Staff/Principal Engineer - Design Verification (SoC expert/lead)
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CS or equivalent, 10+ years SoC verification experience, expert SystemVerilog and UVM, experience developing SoC test plans, emulation exposure, and leadership in complex verification programs.
SystemVerilog, UVM, Gen-AI
3w
Save
Mark Applied
Hide
Principal SoC Integration Flow Architect - Automation
San Jose or San Diego
$211k-$286k/yr OnsiteFull Time
8+ YOEExpertise in SoC integration and RTL design, scripting (Python/Perl/Tcl/C++), familiarity with IP-XACT and EDA integration; 8+ years experience preferred.
Python, Perl, Tcl, C++, IP-XACT, Verilog, SystemVerilog
Explore Jobs