17 uvm jobs at 9 companies in Garland, TX
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Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
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Principal Digital Verification Engineer
Plano, Texas, United States
OnsiteFull Time
8+ YOE8+ years in verification; MS in Electrical/Computer Engineering or equivalent; BS with 10+ years; UVM and SystemVerilog experience; DDR5 verification
UVM, SystemVerilog, Verilog, DDR5
1mo
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Sr Principal Mixed Signal Verification Engineer
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, proficiency in UVM, Spice/Spectre, VerilogAMS, strong debugging and communication skills; Python/shell and SV assertions preferred.
UVM, TLDV UVM, RNM, VerilogAMS, Spice, Spectre, Python, shell, SV-UDN, EENET, SV Assertions
3w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
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Sr. Mixed Signal Design Verification Manager
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, team management experience, hands-on UVM and mixed-signal verification, Spice/Spectre and simulator expertise, strong problem-solving and communication skills.
UVM, VerilogAMS, RNM, Spice/Spectre, Python, shell, SV Assertions, SV-UDN/EENET
1d
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Principal Design Verification Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
10+ YOEBachelor's degree or equivalent experience; 10+ years in digital or mixed-signal design verification; expertise in SystemVerilog, UVM, SVA, coverage-driven verification, ASIC/SoC or memory designs, and AI-assisted verification.
SystemVerilog, UVM, HSPICE, FineSim, Verilog, Python, Perl
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Mixed-Signal Verification Engineer – Analog IP
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
6+ YOEBachelor’s or Master’s degree in Electrical Engineering or related field; 6+ years in mixed-signal or digital IC verification; SystemVerilog and UVM proficiency; Verilog-A/AMS modeling; analog IP verification within digital-on-top SoCs.
SystemVerilog, UVM, Verilog-A/AMS, analog and mixed-signal simulation tools
1d
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Principal Design Verification Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
10+ YOEBachelor's degree in electrical or computer engineering, or equivalent experience, plus 10+ years in digital or mixed-signal design verification. Requires SystemVerilog, UVM, SVA, coverage-driven verification, debugging, and AI-assisted verification expertise.
SystemVerilog, UVM, HSPICE, FineSim, Verilog, Python, Perl
1w
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Mixed Signal Design Verification (MSDV) Engineer
Dallas, Texas, United States
OnsiteFull Time
Bachelor's, master's, or PhD in electrical engineering or related field; analog, digital, and mixed-signal verification experience; Verilog, SystemVerilog, UVM, scripting, EDA tools, and strong analytical skills.
Cadence Virtuoso, Verilog, Verilog-A, SystemVerilog, Universal Verification Methodology (UVM), Unix shell, TCL, Perl, Python, SKILL, I2C, PMBus, SPI, DesignSync, SVN, Git
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ICT (In-Circuit-Test) Engineer
Dallas or Houston
$45k-$121k/yr OnsiteFull Time
3+ YOE3+ years VLSI experience; perform VLSI system development, module/IP verification, UVM-based testbench creation, debugging, and client documentation; mandatory VLSI board design skill.
Universal Verification Methodology (UVM), SharePoint, JIRA, Trend Nxt
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Utility Forester
Dallas, Texas, United States
FieldFull Time
Perform UVM inspections, identify tree/brush control needs, audit contractor work; requires practical tree work experience, tree identification skills, ISA certification (or obtain in 6–12 months), commercial pesticide applicator license, valid driver’s license, and computer proficiency.
Microsoft Word, Microsoft Excel, Microsoft Access, Microsoft Outlook, Microsoft PowerPoint
3w
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Senior Principal Firmware Engineering Lead
McKinney, Texas, United States
$132k-$252k/yr OnsiteFull Time
10+ YOEActive transferable DoD Secret clearance, U.S. citizenship, STEM degree, ~10+ years FPGA/ASIC firmware experience with VHDL/Verilog, leadership, and system-level FPGA design and verification skills.
Xilinx, Altera, Microsemi, VHDL, Verilog, System Verilog, UVM, Veloce, ARM, Microblaze, Nios, High Level Synthesis (HLS)
3d
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FPGA Engineer II
Plano, Texas, United States
$69k-$131k/yr OnsiteFull Time
2+ YOESTEM degree and 2+ years relevant experience, with FPGA/ASIC design or verification, vendor devices and tools, lab integration, Git, Python or C, CI/CD, and digital simulation experience.
AMD, Altera, Microchip, AMD Vivado, Altera Quartus Prime Pro, Libero, VHDL, Verilog, SystemVerilog, Git, Python, C, CI/CD, Questa, RivieraPro, ARM, Microblaze, NIOS, UVM, High Level Synthesis (HLS), GPUs, AES, RSA, ECC
1mo
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FPGA Engineer I
McKinney, Texas, United States
$57k-$109k/yr OnsiteFull Time
0+ YOESTEM bachelor’s required typically; less than 2 years relevant experience; FPGA/ASIC design or verification (VHDL/Verilog/SystemVerilog); experience with AMD Vivado, Altera Quartus Prime Pro, or Libero; lab integration and debug; source control and design reviews.
VHDL, Verilog, SystemVerilog, AMD Vivado, Altera Quartus Prime Pro, Libero, UVM, High Level Synthesis (HLS)
2w
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Senior ASIC/FPGA Design Engineer
McKinney, Texas, United States
$87k-$165k/yr OnsiteFull Time
5+ YOEBachelor's in STEM,5+ years FPGA/ASIC design and RTL experience,experience with Xilinx/Altera and high-speed interfaces,Python/Perl/Shell scripting,ability to obtain U.S. government security clearance;U.S. citizenship required.
Xilinx, Altera, Python, Perl, Shell, System Verilog, UVM, MATLAB, PCI/PCIe, VPX, Gb Ethernet, Ienterlaken
1w
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Digital IC Design Engineer - USB Products
Dallas, Texas, United States
OnsiteFull Time
2+ YOEBachelor's in Electrical/Computer Engineering, 2 years digital design experience, Verilog experience, understanding of digital logic and ASIC design flow, and strong problem-solving skills.
Verilog, System Verilog, AMS, UVM, Perl, Tcl, Python
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