20 uvm jobs at 10 companies in Mesquite, TX
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Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
2mo
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Principal Digital Verification Engineer
Plano, Texas, United States
OnsiteFull Time
8+ YOE8+ years in verification; MS in Electrical/Computer Engineering or equivalent; BS with 10+ years; UVM and SystemVerilog experience; DDR5 verification
UVM, SystemVerilog, Verilog, DDR5
1mo
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Sr Principal Mixed Signal Verification Engineer
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, proficiency in UVM, Spice/Spectre, VerilogAMS, strong debugging and communication skills; Python/shell and SV assertions preferred.
UVM, TLDV UVM, RNM, VerilogAMS, Spice, Spectre, Python, shell, SV-UDN, EENET, SV Assertions
3w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
2w
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Sr Principal Mixed Signal Verification Engineer
Richardson, Texas, United States
OnsiteFull Time
15+ YOEBachelor’s degree in electrical engineering or related field and 15+ years of AMS design or verification experience. Requires UVM, mixed-signal simulation, power-management IC, debugging, and collaboration expertise.
UVM, RNM, VerilogAMS, Spice, Spectre, Python, SV-UDN, EENET, SV Assertions, AI
1mo
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
1mo
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Senior Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
4+ YOEExpert SystemVerilog and UVM skills, testbench development, verification planning, scripting (Python, Perl, TCL), mixed-signal verification, debugging, and technical leadership; Bachelor’s required, 4+ years relevant experience.
SystemVerilog, UVM, Python, Perl, TCL
1mo
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Full Time Raytheon 2026 - Digital Design Electrical Engineer II
McKinney, Texas, United States
$69k-$131k/yr OnsiteFull Time
Master's in EE/Computer Engineering or related STEM, experience with FPGAs (Xilinx/Altera), RTL design (Verilog/VHDL), UVM, scripting (Python/Perl/Shell), waveform/log debugging, and ability to obtain/maintain U.S. security clearance (Secret).
Xilinx, Altera, Verilog, VHDL, UVM, Python, Perl, Shell
1w
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Mixed Signal Design Verification (MSDV) Engineer
Dallas, Texas, United States
OnsiteFull Time
Bachelor's, master's, or PhD in electrical engineering or related field; analog, digital, and mixed-signal verification experience; Verilog, SystemVerilog, UVM, scripting, EDA tools, and strong analytical skills.
Cadence Virtuoso, Verilog, Verilog-A, SystemVerilog, Universal Verification Methodology (UVM), Unix shell, TCL, Perl, Python, SKILL, I2C, PMBus, SPI, DesignSync, SVN, Git
2mo
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ICT (In-Circuit-Test) Engineer
Dallas or Houston
$45k-$121k/yr OnsiteFull Time
3+ YOE3+ years VLSI experience; perform VLSI system development, module/IP verification, UVM-based testbench creation, debugging, and client documentation; mandatory VLSI board design skill.
Universal Verification Methodology (UVM), SharePoint, JIRA, Trend Nxt
1mo
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Utility Forester
Dallas, Texas, United States
FieldFull Time
Perform UVM inspections, identify tree/brush control needs, audit contractor work; requires practical tree work experience, tree identification skills, ISA certification (or obtain in 6–12 months), commercial pesticide applicator license, valid driver’s license, and computer proficiency.
Microsoft Word, Microsoft Excel, Microsoft Access, Microsoft Outlook, Microsoft PowerPoint
2mo
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ASIC & FPGA Design Engineer Sr
Grand Prairie, Texas, United States
$101k-$201k/yr HybridFull Time
3+ YOEBachelor's in EE or related (Master's preferred); 3+ years FPGA design and verification experience; proficiency in VHDL/Verilog/SystemVerilog, FPGA toolsets (Vivado/Vitis), simulation (Synopsys VCS), GitLab; U.S. citizenship and ability to obtain DoD Secret clearance.
VHDL, Verilog, SystemVerilog, UVM, SystemC, Python, GitLab, Vivado, Vitis, Vitis HLS, Synopsys VCS, Synopsys EDA tools, C/C++, MATLAB/Simulink, Synopsys Synplify, NCSim, ChipScope, tcpdump, Wireshark, UltraScale
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