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239 verification engineer jobs at 53 companies in Cedar Park, TX

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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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2mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
Verilab
Verilab: Provides specialized functional verification services for ASIC and FPGA designs.
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
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3mo
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
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1mo
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Verification Engineer Senior
Austin, Texas, United States
$191k-$269k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
6+ YOEBachelor's in EE/CE/CS + 8+ yrs or Master's + 6+ yrs in ASIC/FPGA verification; SystemVerilog/UVM, OOP, coverage-driven verification, constrained-random testing, protocol experience (AXI, CHI, UART, SPI, I2C/I3C), strong debug skills.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium
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2mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Retym
Retym: Developing coherent DSP silicon for AI data center infrastructure.
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
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1mo
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Senior Verification Engineer
Austin, Texas, United States
OnsiteFull Time
NXP Semiconductors
NXP SemiconductorsNASDAQ: NXPI: Designs and manufactures semiconductors for automotive and IoT applications.
5+ YOEBSEE+5yrs or MSEE+3yrs or PhD+1yr; expertise in Verilog/SystemVerilog, OVM/UVM, formal methods; knowledge of DDR, PCIe, AMBA; scripting in Python/Perl and UNIX/Linux; strong debugging and verification planning skills.
Verilog, SystemVerilog, VHDL, OVM/UVM, SystemVerilog assertions (SVA), DDR, PCIe, AMBA (CHI, ACE, AXI), AI/LLM, Python, Perl, UNIX/Linux
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2mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
2+ YOEBS/MS in Electrical/Computer Engineering or equivalent, 2+ years verification experience, SystemVerilog/UVM, Perl or Python scripting, experience with synthesis/simulation and debug tools, strong debugging and collaboration skills.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
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4w
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Renesas Electronics
Renesas ElectronicsTokyo Stock Exchange: 6723: Designs and manufactures semiconductors for automotive and industrial systems.
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
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2w
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Formal Design Verification Engineer
Raleigh or Austin or Hillsboro or Mountain View or Redmond
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOEDegree in EE/CS or equivalent plus technical engineering experience; formal verification, protocol and IP verification experience; ability to pass Microsoft Cloud Background Check and export-control screening.
Coherent Hub Interface (CHI), Advanced Microcontroller Bus Architecture (AMBA), PCIe, CXL, Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), Python
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4w
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
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2mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
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1mo
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Senior ASIC Verification Engineer
Austin or Santa Clara
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOEBachelors/Masters in CS/CE/EE (or equivalent experience), 5+ years experience, SystemVerilog OOP, verification methodology (UVM), VCS/Debussy/GDB exposure, experience with random stimulus, functional coverage, assertions, firmware/hardware verification.
SystemVerilog, VCS, Debussy, GDB, UVM, C, RISC-V Assembly
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1mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
Olix
Olix: Developing optical hardware for artificial intelligence inference.
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
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1w
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Ericsson
EricssonNasdaq: ERIC: Manufactures telecommunications equipment and provides networking services.
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
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1w
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ASIC SoC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Ericsson
EricssonNasdaq Stockholm: ERIC B: Global provider of telecommunications equipment and services.
Experience in SoC/IP/Subsystem verification, SystemC/TLM and RTL verification, hardware emulation familiarity, strong problem-solving and communication; BS required (MS preferred).
SystemC, TLM, RTL, hardware emulation
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1mo
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Staff Verification Engineer
Austin, Texas, United States
$191k-$259k/yr HybridFull Time
Arm
ArmNASDAQ: ARM: Designs and licenses processor architectures and semiconductor intellectual property.
5+ YOE5+ years verifying PCIe/CXL subsystems or SoCs; strong digital design and Verilog/SystemVerilog skills; UVM expertise; experience with simulation/emulation, performance analysis, and testplan creation.
SystemVerilog, Verilog, UVM, Perl, Python
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1mo
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Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Verify high-throughput cellular baseband modems and transceiver link controllers; strong problem solving and technical aptitude for complex engineering challenges.
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2mo
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Design Verification Engineer (Einfochips)
Austin or San Jose
OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
6+ YOE6+ years in System Verilog HVL and C/C++, 6+ years in UVM; strong testbench development, debug, and verification closure; experience with DSP, scripting, and version control tools.
SystemVerilog, HVL, C, C++, UVM, SVTB, Make, Perl, Python, Bugzilla, Subversion
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1mo
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CPU Verification Engineer (RISC-V)
Santa Clara or Austin
$167k-$251k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
2+ YOEExperience validating CPU and SoC micro-architectures (RISC-V preferred), developing test plans/testbenches and verification environments, executing regressions and debug. Bachelor's in EE/CE/CS +4 yrs (or MS+3/PhD+2) in related engineering.
RISC-V, Assembly, Simulators, Gate-level Simulation, Waveform viewers
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1mo
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Principal Engineer, Design Verification Engineering
Austin, Texas, United States
$198k-$251k/yr HybridFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
10+ YOEMaster's in EE/CE (or equivalent) and 10+ years verification experience; expertise in System Verilog, UVM/OVM, Verilog, C/C++, Perforce or Git, EDA tools, scripting (Python/Perl/Shell), and pre/post-silicon verification including ARM or RISC-V subsystems.
System Verilog, UVM, OVM, Verilog, C, C++, Perforce, Git, EDA tools, Python, Perl, Shell
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