2w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
1mo
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Verification Engineer Senior
Austin, Texas, United States
$191k-$269k/yr HybridFull Time
6+ YOEBachelor's in EE/CE/CS + 8+ yrs or Master's + 6+ yrs in ASIC/FPGA verification; SystemVerilog/UVM, OOP, coverage-driven verification, constrained-random testing, protocol experience (AXI, CHI, UART, SPI, I2C/I3C), strong debug skills.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium
1mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
3mo
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Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS with 10+ years in digital verification; SystemVerilog, UVM, Python/Perl; SOC/IP verification experience; strong communication.
SystemVerilog, UVM, Python, Perl, C/C++, Digital design, Scripting
1mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
2mo
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Staff Verification Engineer
Austin or Santa Clara
OnsiteFull Time
5+ YOE+5 years experience; BS/MS in CS/EE/CE; CPU verification; test plans and benches; IP verification; strong analytical skills.
SystemVerilog, C++, Python, Testbench
1mo
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Senior Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBSEE+5yrs or MSEE+3yrs or PhD+1yr; expertise in Verilog/SystemVerilog, OVM/UVM, formal methods; knowledge of DDR, PCIe, AMBA; scripting in Python/Perl and UNIX/Linux; strong debugging and verification planning skills.
Verilog, SystemVerilog, VHDL, OVM/UVM, SystemVerilog assertions (SVA), DDR, PCIe, AMBA (CHI, ACE, AXI), AI/LLM, Python, Perl, UNIX/Linux
3w
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Director, Central AMS Verification
San Jose or Austin or Irvine
$170k-$340k/yr OnsiteFull Time
20+ YOE20+ years in mixed-signal SoC verification, Bachelor’s in CS/CE or related, expert in AMS verification methodologies (UVM, real-number modeling), Python automation, AI/ML for verification, and proven leadership building verification teams.
UVM, Python, Palladium, Veloce, Zebu
2mo
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Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
16h
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Silicon Design Verification Manager
Austin, Texas, United States
$192k-$278k/yr HybridFull Time
8+ YOE8+ years verification experience, degree in EE/CS/CE, expertise in advanced verification methodologies, processor architecture, System Verilog or C++, testbench design, and simulation-based verification.
System Verilog, C++
3mo
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Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
0+ YOEBachelor/Master/PhD in Electrical/Computer Engineering or related field; 2+ years with Bachelors; strong HDL/SystemVerilog/UVM; ASIC/silicon verification experience.
Verilog, VHDL, SystemVerilog, UVM
1d
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Design Verification Architect / Director
San Jose or Austin
$179k-$332k/yr OnsiteFull Time
17+ YOE17+ years verification experience, BS in EE/Computer Engineering, proven people management, expertise in computer architecture, System Verilog, UVM, scripting, assembly, and verification flows.
System Verilog, UVM, Perl, Unix shell, Assembly language, Formal Verification, Gate Level Simulations
3w
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
2mo
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Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
1mo
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Senior ASIC Verification Engineer
Austin or Santa Clara
$136k-$265k/yr HybridFull Time
5+ YOE5+ years experience; BS/MS in CS/CE/EE or equivalent experience; strong verification methodology skills, SystemVerilog OOP, UVM, VCS, debug tools (Debussy, GDB); firmware verification and strong communication.
SystemVerilog, VCS, Debussy, GDB, UVM, C, RISCV Assembly, RISCV
2mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
3w
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Director, Central AMS Verification
San Jose or Austin or Irvine
$170k-$340k/yr OnsiteFull Time
20+ YOEBachelor's in CS/CE or related,20+ years mixed-signal SoC verification experience,expertise in AMS/UVM,proficiency with Python and enterprise verification tools,team leadership and AI/ML application in verification.
UVM, Python, Palladium, Veloce, Zebu
1mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++