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116 asic engineer jobs at 12 companies in Poway, CA

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ASIC Methodology Engineer
Santa Clara or San Diego
$153k-$230k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
3+ YOEMS/PhD or BS with experience in ASIC/VLSI design flows; strong Python skills; hands-on STA experience with PrimeTime or Tempus; problem-solving and analytics; version control experience preferred.
Python, PrimeTime, Tempus, Perforce, Git, GPT, Liama
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1mo
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Sr Principal ASIC Design Engineer - Terawave
San Diego or California or Austin or Texas or Kent
$308k-$431k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
15+ YOEExperienced ASIC/SoC design and verification engineer with expertise in Verilog/SystemVerilog, DSP structures, ARM integration, interface protocols, FPGA flows, post-silicon bring-up; BS/MS in EE or related and 15+ years experience required.
Verilog, SystemVerilog, MATLAB, SystemC, C
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1mo
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ASIC Design Engineer I, Satellite Communications
San Diego, California, United States
$123k-$170k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
2+ YOEBachelor's in Electrical Engineering; 2+ years in digital logic/DSP design; RTL implementation; DSP algorithms optimization.
MATLAB, RTL, UVM, SystemC, DPI-C, Verilog, VHDL
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2mo
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Senior Principal Engineer Digital ASIC Design/Manager
San Diego, California, United States
$214k-$348k/yr OnsiteFull Time
Kyocera
KyoceraTokyo Stock Exchange: 6971: Manufactures advanced ceramic components and high-tech electronic equipment.
15+ YOEBS or MS in Electrical Engineering; 15 years in Digital ASIC design; leadership; cross-functional collaboration; RTL/verification; experience with mixed-signal interfaces is a plus.
Verilog, SystemVerilog, LINT, LEC, RDC/CDC, SDF, Genus, Conformal, Innovus, Spyglass Lint, TetraMax, Xcelium, Cadence, Synopsys PrimeTime, VCS, UGV, UVM
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Cellular ASIC Design Engineer
Austin or San Diego or Sunnyvale
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
10+ YOEBS + 10+ years in RTL-to-GDSII flows; PPA optimization for SoCs; power, performance, area, and co-optimization; strong scripting and ML analytics.
DC/DCT/DCG, Genus, Oasis, ICC2, Fusion, Innovus, Aprisa, PT/PT-SI/Tempus, HSPICE, Finesim, AFS, Spectre, Infinisim, RedHawk, SeaHawk, Voltus, Python, Perl, TCL, Unix shell, C/C++
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Principal Engineer, ASIC/VLSI Synthesis and Design
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
5+ YOE10-15 years in ASIC implementation and synthesis; strong RTL-to-GDSII flow; experience with UPF, ECOs, STA; 5-10 years on advanced nodes; scripting.
Fusion Compiler, Conformal ECO, Conformal Low Power, UPF, Scripting (Tcl, Python)
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ASIC Design Verification Engineer (All Levels)
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
Marvell Technology
Marvell TechnologyNASDAQ: MRVL: Developing semiconductor solutions for cloud, enterprise, and AI infrastructure.
4+ YOEBS/ MS/ PhD with 2-10+ years verification experience; SystemVerilog/UVM; test planning and coverage; Python/Perl; Linux; C++/ARM; networking knowledge a plus.
SystemVerilog, UVM, Python, Perl, EDA tools, Linux, C++, ARM assembly
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ASIC Design Verification Technical Leader
Carlsbad or Allentown
$164k-$235k/yr OnsiteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
8+ YOEBachelor's or higher in Electrical/Computer Engineering; 8+ years ASIC design verification or 6+ with masters; strong SystemVerilog/UVM; leadership experience; scripting (Python, Perl, TCL, Shell).
SystemVerilog, UVM, Python, Perl, TCL, Shell
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1mo
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Electrical Engineer, ASIC Program Lead-CA
San Diego, California, United States
$160k-$200k/yr OnsiteFull Time
Synchron
Synchron: Developing implantable brain-computer interfaces to restore functional independence.
12+ YOE12+ years experience with end-to-end custom ASIC/SoC development, mixed-signal and analog front-end expertise, strong digital design and verification experience, EE degree (BS required, MS preferred), lab debugging skills, and cross-functional collaboration.
Verilog, VHDL, SystemVerilog, UVM, EDA tools, Python, MATLAB, C/C++, Tcl, oscilloscopes, logic analyzers, spectrum analyzers, signal generators, precision measurement equipment, custom test fixtures
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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2mo
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Principal Analog Design Engineer
San Diego, California, United States
$175k-$240k/yr OnsiteFull Time
Elevate Semiconductor
Elevate Semiconductor: Designs integrated circuits for automated semiconductor test equipment.
20+ YOE5+ MgmtMaster’s or PhD in Electrical Engineering; 20+ years MSEE or 15+ years PhD in analog/mixed-signal IC design; leadership in analog ASICs; high-voltage analog design; MATLAB/Simulink/Verilog-A modeling; cross-functional collaboration.
MATLAB, Simulink, Verilog-A, Octave
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GPU Design Verification Engineer
San Diego, California, United States
$180k-$301k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
10+ YOEMS/PhD or equivalent,10+ years ASIC design verification experience,SystemVerilog/UVM,constrained random,functional coverage,hw/sw co-simulation,emulation,strong debugging and GPU architecture knowledge.
SystemVerilog, UVM, emulation
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
BAE Systems
BAE SystemsLondon Stock Exchange: BA: Provides advanced defense, aerospace, and security technology solutions.
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
Siemens
SiemensXETRA: SIE: Manufactures industrial automation, infrastructure, and energy technology systems.
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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