3mo
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RTL Design Engineer
San Diego, California, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; strong RTL design, Verilog/SystemVerilog, DSP concepts, and lab bring-up experience; verification and scripting familiarity.
Verilog, SystemVerilog, Python, Perl, Linter, Clock-domain crossing checkers, Synthesis, Static timing analysis, DFT, Assertions
2mo
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Processor ASIC RTL Design Engineer
San Diego, California, United States
$127k-$191k/yr OnsiteFull Time
2+ YOE2+ years RTL and microprocessor design experience; strong RTL design in System Verilog/Verilog, familiarity with linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC, and low-power techniques; BS/MS/PhD in EE/CS/CE or related.
System Verilog, Verilog, RTL, GDS2, linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC
3w
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Staff/Sr. Staff GPU Engineer – Shader System RTL Design/Microarchitecture
San Diego, California, United States
$150k-$244k/yr OnsiteFull Time
8+ YOEBS/MS/PhD or equivalent,8+ years (Staff) /10+ years (Sr Staff) in RTL/microarchitecture for GPU or high-performance SoC; strong SystemVerilog/Verilog/VHDL,C/C++,Python skills; RTL debug, PPA optimization, and cross-team collaboration.
SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, Shell, Vulkan, Direct3D, OpenGL, OpenGL ES, Metal, OpenCL
1mo
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ASIC Design Engineer I, Satellite Communications
San Diego, California, United States
$123k-$170k/yr OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years in digital logic/DSP design; RTL implementation; DSP algorithms optimization.
MATLAB, RTL, UVM, SystemC, DPI-C, Verilog, VHDL
2mo
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Programmable Logic Design Engineer
Germantown or Carlsbad or Independence or Englewood
$156k-$246k/yr OnsiteContract
5+ YOEBachelor's degree in Electrical/Computer Engineering; 5-8 years FPGA design; SystemVerilog; RTL design for signal processing; FPGA modules; strong communication; distribution teamwork.
System Verilog, Verilog, VHDL, Xilinx Vivado, RTL design, FPGA design, Testbench development, Simulation
2mo
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Distinguished Engineer - Digital Design
San Diego, California, United States
$212k-$314k/yr OnsiteFull Time
17+ YOESenior-level expertise in SystemVerilog, RTL design, PCIe/CXL, and complex SoC architectures; 17+ years (or 12-15 with MS, or 10-12 with PhD); strong leadership and communication.
SystemVerilog, RTL, SVA, Synthesis, Formal verification, Debug tooling, Python, Perl, Tcl, Unix shell
3mo
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Digital Design Engineer
San Diego, California, United States
$190k-$220k/yr OnsiteFull Time
8+ YOELead digital design and verification, RTL synthesis, low-power audio processing, 8+ years in digital blocks for high-performance mixed-signal ICs; strong EDA (Cadence) knowledge.
Cadence, Conformal, Genus, Tempus
2mo
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Staff Digital Design Engineer
San Diego, California, United States
$139k-$232k/yr OnsiteFull Time
6+ YOEDesign digital subsystems for phased array and communication systems; RTL/SystemVerilog; SoC integration; embedded software in C; timing analysis; ECOs; SPI/QSPI and high-speed serial interfaces; Bachelor's or Master's in Electrical Engineering; 6+ years digital ASIC/SoC design.
SystemVerilog, Verilog, C, SPI, QSPI, JESD204B/C, Synthesis, Place-and-Route, UVM, ECOs, RISC-V, embedded software
2mo
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Principal DFT Engineer
Carlsbad, California, United States
$155k-$193k/yr OnsiteFull Time
9+ YOELead DFT on SOC; design/verify DFT; optimize test yield and cost; mentor team.
Verilog, VHDL, RTL, ATPG, MBIST, JTAG, DC/AC analysis, Synthesis, Simulation, ATE
2w
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
1mo
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Field Application Engineer – PowerPro - Job Detail | Careers Marketplace - Siemens
Austin or Costa Mesa or Santa Clara or San Diego
$147k-$293k/yr HybridFull Time
Strong RTL design experience (Verilog/SystemVerilog/VHDL), knowledge of digital design and synthesis/verification flows, RTL power analysis experience, scripting (Tcl, Python), BS/MS in EE/CS or related field, strong communication and problem-solving skills.
PowerPro, Verilog, SystemVerilog, VHDL, Tcl, Python, PrimePower, PowerArtist, UPF, CPF, Microsoft Copilot, OpenAI APIs
1mo
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Senior React.Js Developer - Ecommerce Domain
Chennai or Bengaluru or Porto or Aveiro or Coimbra or Leicester or San Diego
HybridFull Time
Senior React.js developer with expertise in React.js, TypeScript, JavaScript, frontend architectures, state management (Redux/Context API/Zustand), Next.js preferred, testing (Jest, RTL, Cypress/Playwright), Git, CI/CD, and mandatory e-commerce domain experience.
React.js, TypeScript, JavaScript (ES6+), HTML5, CSS3, SCSS, Redux, Redux Toolkit, Context API, Zustand, Next.js, Jest, React Testing Library, Cypress, Playwright, Git, GitHub, GitLab, Bitbucket, RESTful APIs, GraphQL, CI/CD, Tailwind CSS, AWS, Azure, GCP
5d
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Machine Learning and Multimedia IP Verification Manager, Silicon
San Diego or Mountain View
$192k-$279k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE/CS or equivalent; 10 years verifying RTL with SystemVerilog; experience leading verification teams; UVM and OOP experience; strong verification planning and debug skills.
SystemVerilog, UVM, System Verilog Assertions (SVA)
1w
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Sr. Principal Digital Design Verification Lead
San Diego, California, United States
$142k-$213k/yr HybridFull Time
6+ YOEExperience in FPGA verification using SystemVerilog/UVM, Questa/ModelSim, scripting (Python/Tcl/Bash), Git, RTL (Verilog/VHDL); ability to obtain US Secret clearance and Program Access (PAR).
SystemVerilog, UVM, Questa, ModelSim, Verilog, VHDL, SVA, Python, Tcl, Bash, Git
1w
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Sr. Principal Digital Design Verification Lead
San Diego, California, United States
$142k-$213k/yr HybridFull Time
5+ YOE5+ years FPGA verification experience, strong SystemVerilog/UVM skills, Questa/ModelSim experience, RTL knowledge (Verilog/VHDL), scripting (Python/Tcl/Bash), Git, and ability to obtain US Secret clearance and Program Access.
SystemVerilog, UVM, Questa, ModelSim, Verilog, VHDL, SVA, Python, Tcl, Bash, Git
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