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355 asic engineer jobs at 50 companies in Salinas, CA

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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
Ayar Labs
Ayar Labs: Develops optical interconnect technology for high-speed data movement.
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
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Senior ASIC Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
2+ YOE2+ years ASIC verification experience, UVM experience, ability to build UVM testbenches, knowledge of digital logic, SoC architecture, AMBA protocols, scripting, and verification strategy.
UVM, ARM, AMBA, AHB, AXI
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ASIC Design Engineer
Santa Clara or United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
3+ YOEBachelor's degree with 3+ years of ASIC design experience; memory subsystem and RTL knowledge beneficial.
RTL, HDL, DFI, DRAM, Memory subsystem, Performance simulators
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ASIC Implementation Engineer STA
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
12+ YOEBachelor's in EE or Computer Engineering, 12+ years ASIC STA experience, proficiency with Cadence or Synopsys sign-off flows, SDC/constraint development, and scripting in Tcl, Python, or Perl.
Tcl, Python, Perl, Shell, Cadence, Synopsys
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Senior ASIC Design Engineer
Santa Clara or United States
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOE5+ years ASIC or SoC design experience; BS/MS in relevant engineering or equivalent; RTL design, logic synthesis, timing analysis, SOC integration experience; strong scripting/programming (Perl, Python, C++).
Perl, Python, C++
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
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SR ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
1+ YOEDegree in electrical/computer engineering or related plus multi-year ASIC verification experience; proficiency in System Verilog and UVM; ASIC verification, simulation, emulation, post-silicon debug experience; Linux and programming (C/C++, Python/Perl).
System Verilog, UVM, Veloce, Palladium, Zebu, HAPS, Linux, C/C++, Python/Perl
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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
Nokia
NokiaNYSE: NOK: Sells telecommunications infrastructure and software for global network operators.
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
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ASIC/SoC Design Engineer
San Jose or United States
$146k-$250k/yr OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in ASIC/SoC design, RTL/verification, Verilog/SystemVerilog, timing constraints, PD integration, DFT, and cross-domain collaboration.
Verilog, SystemVerilog, SystemVerilog Assertions, SDC timing constraints, ASIC CAD tools, AMBA AXI/AXI-S/APB, UPF, Perl, Python, Makefile
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ASIC Design Verification Engineer
Santa Clara, California, United States
$106k-$172k/yr OnsiteFull Time
Palo Alto Networks
Palo Alto NetworksNASDAQ: PANW: Provides enterprise-grade network, cloud, and endpoint security software.
3+ YOEBS in EE, CE, or CS; minimum 3 years ASIC verification; SystemVerilog/UVM; test plans, coverage, and debug; Python automation; strong collaboration.
SystemVerilog, UVM, Python, C++, Perl, UNIX Shell
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Sr. Staff ASIC Verification Engineer
Sunnyvale or San Jose or Munich
OnsiteFull Time
Tensordyne
Tensordyne: Designs AI chips and systems for efficient model inference.
15+ YOE15+ years ASIC verification experience; expert in SystemVerilog and UVM; experience with SoC/subsystem verification, ARM/RISC-V, high-speed interfaces, C/C++/SystemC; scripting with Python/Perl/Tcl/Shell; BS required, MS preferred.
SystemVerilog, UVM, C, C++, SystemC, Python, Perl, Tcl, Shell
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Senior ASIC Design Engineer – Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
E-Space
E-Space: Builds sustainable LEO satellite networks for global IoT connectivity
7+ YOESenior ASIC/SoC design with processor subsystem integration and RTL expertise.
SystemVerilog, VHDL, AMBA (AHB, APB, AXI), Synopsys VCS, Cadence Xcelium, Mentor Questa
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
Axiado
Axiado: Creates AI-driven security processors for data center infrastructure.
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
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Sr. ASIC Design Engineer
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
5+ YOE5+ years experience; BS in Electrical Engineering or Computer Science; hands-on GenAI and agentic tool experience; proficient with EDA flows, SystemVerilog, simulation, synthesis, static timing analysis and top-level integration; AI/LLMs and interface protocol knowledge desirable.
GenAI, MCP, EDA, SystemVerilog, LLMs, PCIe, NVMe, DRAM, NAND, AXI, APR, DFT, LEC, CDC, linting
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3mo
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ASIC Architect
Santa Clara, California, United States
$192k-$287k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
15+ YOE15+ years in Electrical/Computer Engineering with Masters or 10+ years with PhD; strong architecture leadership; experience with ASIC product architectures; knowledge of PCIe, CXL, UALink, Ethernet; ARM CPU subsystem; hardware/SoC co-design and security.
PCIe, CXL, Ethernet, UALink, Data Network Switching, ARM CPU Subsystem
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
Synopsys
SynopsysNasdaq: SNPS: Provides software and IP for semiconductor design and manufacturing.
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
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ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
ByteDance
ByteDance: Developing AI-driven content platforms and mobile applications.
2+ YOEM.S./Ph.D. in EE/CE, 2+ years ASIC front-end RTL ownership, proficiency in SystemVerilog/Verilog or HLS, familiarity with UVM/DPI/C++, Python scripting, and VLSI design concepts.
SystemVerilog, Verilog, High level Synthesis (HLS), UVM, DPI, C++, Python, AXI, APB, EDA, GitHub Copilot, Claude, ChatGPT, FPGA
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Sr. / Staff ASIC Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
SK hynix Memory Solutions America
SK hynix Memory Solutions AmericaKorea Exchange: 000660: Develops semiconductor controllers and firmware for enterprise data storage.
6+ YOEExpertise in DFT, synthesis, power and timing analysis; tapeout experience; scripting (tcl/perl/python/shell); UPF and STA; Bachelors+8 years or Masters+6 years in engineering.
Synopsys, Siemens Tessent, PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, UPF, UNIX, Linux, tcl, perl, python, shell
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Cupertino or Austin
$157k-$213k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
Bachelor's in Electrical Engineering (required), experience debugging and verifying designs from IP to SoC, proficiency in SystemVerilog, strong analytical and problem-solving skills.
SystemVerilog, Python, Perl
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