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Design Verification Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
10+ YOEBS or higher with 10+ years in digital verification; strong SystemVerilog, verification methodologies (UVM), Python/Perl; hardware/SOC DV experience.
SystemVerilog, Python, Perl, C++, C, UVM, Debugging, Digital Verification
1w
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Staff Engineer, Design Verification Engineering
Wilmington, Massachusetts, United States
$172k-$210k/yr HybridFull Time
4+ YOEMaster's+4yrs or Bachelor's+6yrs in relevant engineering; experience with System Verilog and UVM, metric-driven verification, simulation debug, IP/VIP integration, verification planning, and scripting for automation.
UVM, System Verilog
3mo
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GPU Design Verification Engineer
San Diego or Santa Clara or Boxborough or Austin
$162k-$273k/yr OnsiteFull Time
2+ YOEBachelor's +4 yrs (or Master's +3 / PhD +2) in Comp Eng/CS/EE; experience in hardware/software/systems engineering; verification skills with System Verilog/UVM, Verilog/VHDL, C/C++; scripting and emulation exposure preferred.
System Verilog, UVM, Verilog, VHDL, C/C++, Python, Make, Airflow, Veloce, Palladium, Zebu, FPGA, Protium, HAPS, qemu, GNU Toolchain, Visual Studio, gdb, uboot, uefi, Vulkan, DX11, DX12, Windows, Linux
2mo
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Principal Design Verification Engineer
Morrisville or Westborough
$160k-$237k/yr OnsiteFull Time
10+ YOEVerify SoC design with SystemVerilog/UVM; develop verification environment; write tests; debug issues; strong scripting.
SystemVerilog, UVM, Python, Perl, C++, EDA tools, ARM
1mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
1mo
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Design Verification Engineer, PLM
Portsmouth, New Hampshire, United States
OnsiteFull Time
2+ YOEBachelor's in engineering and 2+ years experience in design, development, and testing; knowledge of design control, validation, and regulatory standards; proficiency with test documentation and engineering change processes.
Azure DevOps, JIRA, Greenlight Guru, SAP
2w
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Senior Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
8+ YOE8+ years ASIC/SoC design verification experience, strong SystemVerilog and Python skills, deep knowledge of cache-coherent interconnects and protocols (CHI, ACE, CXL, AXI), BS/MS in EE/CE/CS, strong communication and leadership.
SystemVerilog, Python
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
3w
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1mo
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Formal Verification Engineer
Austin or Boston or Santa Clara
$156k-$268k/yr HybridFull Time
8+ YOESenior-level role requiring 8+ years in design verification with formal methods; strong SVA and formal verification tool experience; BS/MS in Computer/Electrical Engineering; located in Austin, Boston, or Santa Clara.
VC Formal, JasperGold, SystemVerilog, SVA, TCL, Python, Perl
1mo
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Design Verification & Test Development Engineer
Bedford, Massachusetts, United States
$64k-$92k/yr OnsiteFull Time
3+ YOE3+ years developing and executing test methods for electromechanical products; BS in Engineering; Python and data analysis (Pandas, NumPy, Matplotlib); experience with test equipment (LabVIEW, PLC, Raspberry Pi, HALT/thermal/vibration chambers); strong communication and problem solving.
Python, Pandas, NumPy, Matplotlib, PLC, Raspberry Pi, LabVIEW, C#, HALT chambers, thermal chambers, vibration tables, power analyzers, pneumatics, oscilloscopes, multi-meters, AI
2mo
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Design Verification Test (DVT) Manager
Derry, New Hampshire, United States
$125k-$140k/yr OnsiteFull Time
5+ YOE3+ MgmtBachelor's in engineering; 5 years product validation/certification; 3+ years management in test/verification; knowledge of safety design/test; experience with certifications (UL) and ISO; create test processes/reports; support factory releases.
3mo
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Principal Electrical Engineer-FPGA Verification
Tewksbury or Marlborough
$108k-$205k/yr OnsiteFull Time
8+ YOE8+ years in digital design verification; SystemVerilog; UVM; FPGA verification; DoD/DoD-style security clearance.
SystemVerilog, UVM, AXI, PCIe, Ethernet, DDR, Questa, VCS, Xcelium, Git, ClearCase, SVN, Vivado, Quartus, Python, Tcl, Perl, VHDL, SLURM
1mo
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Mechanical Design Engineer
Hudson, Massachusetts, United States
$80k-$100k/yr OnsiteFull Time
5+ YOEBachelor's in Mechanical Engineering (ABET), 5+ years mechanical design experience, 3+ years SolidWorks, COSMOS experience preferred, heavy-structure and subsystem design, vendor sourcing, verification and validation.
SolidWorks, COSMOS
3mo
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ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA) (North Reading, MA, US)
North Reading, Massachusetts, United States
$99k-$158k/yr OnsiteFull Time
3+ YOE3+ years in digital logic verification; Cadence Xcelium; SystemVerilog and UVM; IP protocols (SPI/AXI/DDR); RTL Verilog; CI/CD workflows.
Cadence Xcelium, SystemVerilog, UVM, Verilog HDL, CI/CD
1mo
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Physical Design Engineer
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
3+ YOEBSEE/MSEE or equivalent; 3+ years VLSI physical design on 5/4/3nm; expertise in P&R, timing closure, power/clock distribution, verification; experience with Synopsys/Cadence EDA tools; Python/Perl/Tcl/Make scripting.
ICC2, DC, PT, STAR, ICV, Genus, Innovus, Tempus, Python, Perl, Tcl, Make
3w
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Functional Verification Applications Engineer - Boston/Baltimore/Raleigh - Job Detail | Careers Marketplace - Siemens
Boston or Burlington or Marlborough or Cary or Baltimore or Raleigh
$125k-$251k/yr HybridFull Time
3+ YOEBachelor's in Engineering/CS (or equivalent) with 3+ years; expertise in ASIC & FPGA design and verification, advanced verification methodologies; coding in Verilog/VHDL/SystemVerilog, UVM, PSL/SVA; familiarity with EDA tools, Verification IP, Formal, Emulation; US citizenship required.
Verilog, VHDL, SystemVerilog, UVM, PSL/SVA, Verification IP, Formal, Emulation, EDA, APIs
3w
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Engineer: Sr. Electrical Design Engineer
Cambridge, Massachusetts, United States
$80k-$110k/yr OnsiteFull Time
5+ YOEMaster's in EE, 5+ years product development experience, PCB and embedded hardware design, Altium/Eagle, C/Assembly, verification/validation, FDA/ISO 13485 experience, LabVIEW/MATLAB/Simulink familiarity.
Altium, Autodesk Eagle, C, Assembly, Verilog, VHDL, FPGA, ASIC, LabVIEW, MATLAB, Simulink, Java, Android, oscilloscopes, logic analyzers
3d
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Senior Optical Design Engineer
Newington, New Hampshire, United States
OnsiteFull Time
8+ YOEMaster's in Optical/Electrical Engineering or Physics, 8+ years optical systems experience, expertise in fiber optics and optical test methods, modeling and prototyping, EDFAs, verification and reliability testing, strong communication and leadership.
LabWindows/CVI
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