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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
3mo
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Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
1mo
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
1mo
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
1mo
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Senior Design Verification Engineer
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
5+ YOE5+ years UVM/System Verilog design verification experience, BS in EE/CS required (MS preferred), GenAI and agentic MCP experience, ASIC simulation and SoC/CPU emulation expertise, System Verilog/System C/C++ skills, test plan and coverage closure experience.
GenAI, agentic MCP, UVM, System Verilog, System C, C++
2mo
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SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
1mo
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Design and Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Degree in EE/CE or related, experience in RTL design and functional verification, proficiency with Verilog/SystemVerilog, UVM, and simulation tools; strong collaboration and AI/ML interest preferred.
Verilog/SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Siemens Questa, Microsoft Excel
3mo
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Design Verification Engineer, Memory Controller
San Jose or Austin
$151k-$252k/yr OnsiteFull Time
6+ YOE10+ years in design verification; 8+ years in testbenches; DDR/LPDDR/HBM; ARM CHI/AXI/ACElite; SystemVerilog/UVM; Git/Unix scripting; strong communication.
SystemVerilog, UVM, ARM CHI, ARM AXI, ACElite, APB, Git, Unix scripting
2mo
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
1mo
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Sr. Design Verification Engineer
San Jose, California, United States
$130k-$160k/yr OnsiteFull Time
7+ YOEBS/MS in EE/CE, 7+ years RTL/functional verification using SV/UVM, PCIe and gate-level experience, firmware-based simulation and C knowledge, strong debugging and scripting (Python/Perl/Shell) skills.
SV, UVM, C, Python, Perl, Shell scripting, PILOT
1mo
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ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
7+ YOEBachelor’s +7 years, or Master’s +4, or PhD +1; SystemVerilog/UVM; verification methodologies incl. emulation; architecture and leadership in verification; scripting (Python, Perl) and C/C++.
SystemVerilog, UVM, emulation, Python, Perl, C/C++
5d
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Design Verification Engineer
San Jose, California, United States
$100k-$120k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS,4+ years verifying digital ASIC/FPGA/SoC using SystemVerilog/UVM,SVA and industry simulators; experience with RTL debug, coverage closure, scripting and revision control.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, Python, Perl, Tcl, Shell, Git, Perforce
1mo
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SoC Physical Design Verification Engineer
San Jose, California, United States
OnsiteFull Time
Experience in physical verification of system-on-chip (SoC) designs and semiconductor implementation; ability to craft solutions for high-performance, power-efficient processors.
2mo
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Design Verification Architect
San Jose or United States
$150k-$300k/yr HybridFull Time
12+ YOEBachelor's/Master's in EE/CE, 12+ years design verification experience for large SoCs, expertise in SystemVerilog, UVM, Portable Stimulus (PSS), coverage-driven and assertion-based verification, and strong architecture and debugging skills.
SystemVerilog, UVM, Portable Stimulus (PSS), PCIe, DDR, Ethernet, CXL, UCIe
2w
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Principle Design Verification Engineer SerDes/PHY
San Jose, California, United States
$207k-$230k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE required, 8+ years verification experience on high-speed SerDes/PHY or mixed-signal IP, expert SystemVerilog/UVM, RNM and analog/mixed-signal co-simulation, protocol knowledge (PCIe/UALink/UCIe/Ethernet/CXL); mentoring and leadership experience.
SystemVerilog, UVM, Real Number Modeling (RNM), Palladium, Veloce, ZeBu, Python, Perl, PCIe, UALink, UCIe, Ethernet, CXL, COSMOS
1mo
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Principal Engineer, AI & ML Design Verification (AI2517)
San Jose, California, United States
$204k-$316k/yr OnsiteFull Time
12+ YOEBS/MS in EE or CS required, 12+ years verification experience with UVM and System Verilog, AMBA knowledge, testbench and coverage development, silicon/emulation debug, strong debugging and problem-solving skills.
UVM, System Verilog, System Verilog Assertion (SVA), AMBA
1mo
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Design Verification Technical Architect
Austin or San Jose or Santa Clara
$150k-$190k/yr OnsiteFull Time
10+ YOE10+ years DV experience; SV-UVM; Python; Verilog; C; high speed protocol (PCIe, UCIe, LPDDR5, Ethernet200G); SS/SOC level verification; source control (git); emulation; Arm core; C-base; test plan development.
SV-UVM, Python, Verilog, C, PCIe, UCIe, LPDDR5, Ethernet200G+, SystemVerilog, RISCV, AMBA, git, Emulation, Arm Core, C-Base
1w
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Physical Design Engineer
San Jose, California, United States
$150k-$250k/yr OnsiteFull Time
7+ YOE7+ years physical design experience (synthesis, PnR, STA, timing convergence, physical verification); Bachelor's in EE/CE/CS or equivalent experience; proficiency with Innovus, Tempus, Quantus, TCL; experience with EM/IR, PDN, LEC and sub-7nm/SoC design.
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
1w
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Technologist, RFIC Design Engineer
San Jose, California, United States
$171k-$227k/yr OnsiteFull Time
Hands-on RF and analog IC design experience in CMOS (40nm and below), transistor/block/module architecture, layout and verification, EDA tool proficiency, and track record of production design releases.
Cadence, Mentor, Siemens, Ansys
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