2mo
Save
Mark Applied
Hide
Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
1w
Save
Mark Applied
Hide
Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
1mo
Save
Mark Applied
Hide
Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
2mo
Save
Mark Applied
Hide
ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
3mo
Save
Mark Applied
Hide
Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
1mo
Save
Mark Applied
Hide
Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
2mo
Save
Mark Applied
Hide
Senior Debug Verification Engineer
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
8+ YOE8+ years ASIC/design verification; SystemVerilog; UVM and formal verification; Linux/Unix scripting with Perl or Python; strong cross-site collaboration.
SystemVerilog, UVM, Formal verification, Linux, Perl, Python, Emulation, JTAG, PCIe, USB
2w
Save
Mark Applied
Hide
Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
2mo
Save
Mark Applied
Hide
SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
1mo
Save
Mark Applied
Hide
Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
1mo
Save
Mark Applied
Hide
Staff Engineer Verification
San Jose, California, United States
$118k-$162k/yr HybridFull Time
1+ YOE1+ years experience in high-speed SI/PI and EMC; degree in a related field; experience with Ansys HFSS, Keysight ADS, VNA/TDR/oscilloscope; Python and MATLAB proficiency; strong communication and teamwork.
Ansys HFSS, Keysight ADS, VNA, TDR, spectrum analyzer, high-speed oscilloscope, Python, MATLAB, S-parameters, IBIS-AMI
1mo
Save
Mark Applied
Hide
ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
7+ YOEBachelor’s +7 years, or Master’s +4, or PhD +1; SystemVerilog/UVM; verification methodologies incl. emulation; architecture and leadership in verification; scripting (Python, Perl) and C/C++.
SystemVerilog, UVM, emulation, Python, Perl, C/C++
1mo
Save
Mark Applied
Hide
Sr. Design Verification Engineer
San Jose, California, United States
$130k-$160k/yr OnsiteFull Time
7+ YOEBS/MS in EE/CE, 7+ years RTL/functional verification using SV/UVM, PCIe and gate-level experience, firmware-based simulation and C knowledge, strong debugging and scripting (Python/Perl/Shell) skills.
SV, UVM, C, Python, Perl, Shell scripting, PILOT
1mo
Save
Mark Applied
Hide
Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
1mo
Save
Mark Applied
Hide
Sr. Staff ASIC Verification Engineer
Sunnyvale or San Jose or Munich
OnsiteFull Time
15+ YOE15+ years ASIC verification experience; expert in SystemVerilog and UVM; experience with SoC/subsystem verification, ARM/RISC-V, high-speed interfaces, C/C++/SystemC; scripting with Python/Perl/Tcl/Shell; BS required, MS preferred.
SystemVerilog, UVM, C, C++, SystemC, Python, Perl, Tcl, Shell
1mo
Save
Mark Applied
Hide
Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
3w
Save
Mark Applied
Hide
Senior Staff Engineer, GPU Design Verification (Formal Verification)
San Jose, California, United States
$198k-$297k/yr OnsiteFull Time
8+ YOE8+ years verification experience (formal verification focus), proficiency in formal methods, System Verilog/SVA, Python/Perl/C++, EDA formal tools, strong debugging and architecture knowledge; BS/MS/PhD in CS/CE/related.
Python, Perl, C/C++, System Verilog, System Verilog Assertions (SVA), Confluence, JIRA, Universal Verification Methodology (UVM), UPF
3mo
Save
Mark Applied
Hide
Integration and Verification Engineer, Turbogenerator
San Jose, California, United States
$172k-$216k/yr OnsiteFull Time
10+ YOEBS/MS/PhD in a related scientific or engineering field; 10+ years in complex system verification; strong systems engineering; experience with turbine and/or electrical systems; ability to meet tight timelines; excellent communication; independent leadership.
Test benches, LabVIEW, Matlab/Simulink, Systems verification, Aerospace testing
2mo
Save
Mark Applied
Hide
Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
1mo
Save
Mark Applied
Hide
SoC Physical Design Verification Engineer
San Jose, California, United States
OnsiteFull Time
Experience in physical verification of system-on-chip (SoC) designs and semiconductor implementation; ability to craft solutions for high-performance, power-efficient processors.
Explore Jobs