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Digital Design Engineer
San Jose, California, United States
$130k-$200k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in EE/CE,5+ years digital RTL design experience,SystemVerilog proficiency,ASIC flow and EDA tool experience,high-speed SerDes/DSP knowledge,Python/MATLAB/C++ familiarity.
System Verilog, Synopsys, Cadence, Siemens, Python, MATLAB, C++
1mo
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Principal Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
5+ YOEBachelor’s or Master’s in Electrical/Computer Engineering or related field; 5-10 years in digital design for high-speed DSP data paths; SystemVerilog coding; experience with Synthesis, Lint, CDC, PrimeTime; RTL delivery; full design cycle; timing/area/power optimization; silicon issue resolution
SystemVerilog, EDA tools, Synthesis, Lint, CDC, PrimeTime
1mo
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Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
2mo
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years in digital/ASIC design with chip/design lead ownership; SystemVerilog RTL; synthesis/timing tools; cross-team integration leadership.
SystemVerilog, DC, Genus, PrimeTime, Tempus
1mo
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Digital Design Engineer - New College Grad
San Jose, California, United States
$99k-$183k/yr HybridFull Time
Master's degree in EE or related field; experience with RTL coding, Verilog models, and analog/digital design; test support and chip bring-up; strong communication and team skills.
Verilog, RTL, Simulations, I2C, SPI, AHB, APB, Bench testing, ATE testing
2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
2mo
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MTS Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
17+ YOEBS EE with 17+ years or MS with 15+ years; strong RTL/Verilog; ASIC/mixed-signal ICs; power management; leadership and cross-functional communication.
Verilog, SystemVerilog, TCL, Python, Perl, XML
6d
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
1mo
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
1w
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SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS or related, 1+ years front-end digital design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile).
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA, FPGA, ASIC
2w
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
3d
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Sr. / Staff ASIC Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
6+ YOEExpertise in DFT, synthesis, power and timing analysis; tapeout experience; scripting (tcl/perl/python/shell); UPF and STA; Bachelors+8 years or Masters+6 years in engineering.
Synopsys, Siemens Tessent, PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, UPF, UNIX, Linux, tcl, perl, python, shell
1w
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Design Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in Electrical/Computer Engineering (or equivalent), 3+ years SystemVerilog RTL design experience, strong digital design fundamentals, power/timing-aware practices, simulation debug, and scripting in Python/Perl/TCL.
SystemVerilog, Python, Perl, TCL, UVM, SVA
4d
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Graduate- Senior Engineer Digital IC Design
San Jose, California, United States
$127k-$174k/yr HybridFull Time
0+ YOEBachelor's degree in CS/EE/CE or related,0-2 years experience,knowledge of Verilog/System Verilog and digital frontend flows,RTL coding,verification/debugging,emphasis on automotive safety;Python/Perl preferred;must be legally authorized to work in the US.
Verilog, System Verilog, Python, Perl
1mo
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Digital Design Specialist: Structural Engineering
San Jose, California, United States
$74k-$99k/yr HybridFull Time
4+ YOE4–15 years in building design with emphasis on structural drafting and BIM; CAD and Revit proficiency; strong collaboration and documentation skills.
CAD, Revit, BIM, Structural Modeling
1mo
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Principal Engineer - Digital ASIC Design
San Jose, California, United States
$70k-$163k/yr OnsiteFull Time
10+ YOE10+ years ASIC/FPGA digital design; SystemVerilog; Cadence/Synopsys front-end; PHY/Serdes knowledge; post-silicon validation; travel up to 25%.
System Verilog, Cadence Tools, Synopsys Tools, VCS, SpyGlass, Design Compiler, PrimeTime, Lab equipment
1mo
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Senior Hardware Design Engineer
San Jose, California, United States
$180k-$200k/yr OnsiteFull Time
8+ YOEBS/MS in EE, 8+ years hardware design experience with high-speed digital PCBs, CMOS image sensor integration, signal/power integrity expertise, technical leadership/mentoring, and experience with Altium Designer or Cadence Allegro and lab debugging instruments.
Altium Designer, Cadence Allegro, oscilloscope, protocol analyzer, logic analyzer, SLVS, SLVS-EC, MIPI CSI-2, USB-C, LVDS
1mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
4d
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Design Verification Engineer
San Jose, California, United States
$100k-$120k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS,4+ years verifying digital ASIC/FPGA/SoC using SystemVerilog/UVM,SVA and industry simulators; experience with RTL debug, coverage closure, scripting and revision control.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, Python, Perl, Tcl, Shell, Git, Perforce
2d
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3D Stacked DRAM-on-Logic Design Engineer
San Jose, California, United States
$150k-$260k/yr OnsiteFull Time
5+ YOEBachelor's in EE,5+ years experience in digital IP/SoC and RTL design for 3D-stacked DRAM,experience with Verilog/VHDL,memory controllers,BIST/DFT/DFD,and strong English communication.
Verilog, VHDL, RTL
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